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| author | Bert Vermeulen <bert@biot.com> | 2012-02-12 14:55:20 +0100 |
|---|---|---|
| committer | Bert Vermeulen <bert@biot.com> | 2012-02-12 14:55:20 +0100 |
| commit | 582c8473ffd456dfb0796974ef2c0b1b78de38a8 (patch) | |
| tree | 7ae052de00e260ab66ee4fec34014eacf553bb7b /type_logic.c | |
| parent | 12243c22bf01506ac3b220bfe38384db9903756c (diff) | |
| download | libsigrokdecode-582c8473ffd456dfb0796974ef2c0b1b78de38a8.tar.gz libsigrokdecode-582c8473ffd456dfb0796974ef2c0b1b78de38a8.zip | |
srd: last public/private fix, and docs for all publis functions.
Diffstat (limited to 'type_logic.c')
| -rw-r--r-- | type_logic.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/type_logic.c b/type_logic.c index 5e499f4..bb4ef3d 100644 --- a/type_logic.c +++ b/type_logic.c @@ -49,8 +49,7 @@ static PyObject *srd_logic_iternext(PyObject *self) logic->inbuf + logic->itercnt * logic->di->data_unitsize, logic->di->data_unitsize); for (i = 0; i < logic->di->dec_num_probes; i++) - probe_samples[i] = - sample & (1 << logic->di->dec_probemap[i]) ? 1 : 0; + probe_samples[i] = sample & (1 << logic->di->dec_probemap[i]) ? 1 : 0; /* Prepare the next samplenum/sample list in this iteration. */ py_samplenum = |