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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2013-01-20 21:26:45 +0100 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2013-01-27 17:53:56 +0100 |
| commit | 322c6b2fb36aaa38967ca797acef0ebb1f3090e6 (patch) | |
| tree | c28dde675c3e3378536584248150710a5bdf9212 /type_logic.c | |
| parent | 6d333fd65c41f7bf6470d0b6ada88efee4777f59 (diff) | |
| download | libsigrokdecode-322c6b2fb36aaa38967ca797acef0ebb1f3090e6.tar.gz libsigrokdecode-322c6b2fb36aaa38967ca797acef0ebb1f3090e6.zip | |
Temporarily revert API changes in preparation of release.
The upcoming libsigrokdecode release should not contain any API changes
so it is compatible with existing released frontends (sigrok-cli 0.3.1).
Diffstat (limited to 'type_logic.c')
| -rw-r--r-- | type_logic.c | 17 |
1 files changed, 1 insertions, 16 deletions
diff --git a/type_logic.c b/type_logic.c index 098e34d..b284ebf 100644 --- a/type_logic.c +++ b/type_logic.c @@ -45,26 +45,11 @@ static PyObject *srd_logic_iternext(PyObject *self) * Convert the bit-packed sample to an array of bytes, with only 0x01 * and 0x00 values, so the PD doesn't need to do any bitshifting. */ - - /* Get probe bits into the 'sample' variable. */ memcpy(&sample, logic->inbuf + logic->itercnt * logic->di->data_unitsize, logic->di->data_unitsize); - - /* All probe values (required + optional) are pre-set to 42. */ - memset(probe_samples, 42, logic->di->dec_num_probes); - /* TODO: None or -1 in Python would be better. */ - - /* - * Set probe values of specified/used probes to their resp. values. - * Unused probe values (those not specified by the user) remain at 42. - */ - for (i = 0; i < logic->di->dec_num_probes; i++) { - /* A probemap value of -1 means "unused optional probe". */ - if (logic->di->dec_probemap[i] == -1) - continue; + for (i = 0; i < logic->di->dec_num_probes; i++) probe_samples[i] = sample & (1 << logic->di->dec_probemap[i]) ? 1 : 0; - } /* Prepare the next samplenum/sample list in this iteration. */ py_samplenum = |