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authorGerhard Sittig <gerhard.sittig@gmx.net>2017-07-02 12:39:08 +0200
committerUwe Hermann <uwe@hermann-uwe.de>2017-07-04 12:01:04 +0200
commit45a5088085c07c862549ad820d752a46ef0e0c76 (patch)
tree6ff69adb5c9bf370fe8baa07a05e2697f1bf1525 /tests/session.c
parent300f9194250913babbd57d5eccc2ceccf9010785 (diff)
downloadlibsigrokdecode-45a5088085c07c862549ad820d752a46ef0e0c76.tar.gz
libsigrokdecode-45a5088085c07c862549ad820d752a46ef0e0c76.zip
can: introduce clock synchronization (simple implementation)
Check for falling edges (i.e. changes to dominant state) between bits of a CAN frame, and adjust subsequent bit slots' sample points accordingly. This is a simple implementation which could get improved later. But it improves the decoder's reliability when the input signal's rate differs from the nominal rate. This fixes bug #990. Reported-By: PeterMortensen via IRC
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