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authorGerhard Sittig <gerhard.sittig@gmx.net>2017-06-18 20:02:46 +0200
committerUwe Hermann <uwe@hermann-uwe.de>2017-06-21 17:45:15 +0200
commitfcbd63364b64383c437c6182110557ac30201a1f (patch)
tree92053bb6b79704f7d6101df4e878e2c4cf5877fc /decoders
parenta912e8cbb6ab4a56bee71a9c0fd0045d5fdee55c (diff)
downloadlibsigrokdecode-fcbd63364b64383c437c6182110557ac30201a1f.tar.gz
libsigrokdecode-fcbd63364b64383c437c6182110557ac30201a1f.zip
ir_rc5: Rephrase open coded value for start bit 1
Make obvious that the start bit's value is 1 in the IDLE stage.
Diffstat (limited to 'decoders')
-rw-r--r--decoders/ir_rc5/pd.py3
1 files changed, 2 insertions, 1 deletions
diff --git a/decoders/ir_rc5/pd.py b/decoders/ir_rc5/pd.py
index ae29f10..edb29bd 100644
--- a/decoders/ir_rc5/pd.py
+++ b/decoders/ir_rc5/pd.py
@@ -147,8 +147,9 @@ class Decoder(srd.Decoder):
# State machine.
if self.state == 'IDLE':
+ bit = 1
self.edges.append(self.samplenum)
- self.bits.append([self.samplenum, 1])
+ self.bits.append([self.samplenum, bit])
self.state = 'MID1'
self.old_ir = self.ir
continue