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authorUwe Hermann <uwe@hermann-uwe.de>2020-01-08 23:21:54 +0100
committerUwe Hermann <uwe@hermann-uwe.de>2020-01-09 00:15:02 +0100
commitde5a2d286ecf1f8feeb149a0c96d1831d167a080 (patch)
tree2dc151fc165084e7570c8c37f0bb84bbdffa64b8 /decoders
parent7aab31bb8a46aeaded3ba682cc3ebfc22a70dbcd (diff)
downloadlibsigrokdecode-de5a2d286ecf1f8feeb149a0c96d1831d167a080.tar.gz
libsigrokdecode-de5a2d286ecf1f8feeb149a0c96d1831d167a080.zip
cjtag: Drop non-existing channels from the decoder.
cJTAG only has two wires/channels.
Diffstat (limited to 'decoders')
-rw-r--r--decoders/cjtag/pd.py17
1 files changed, 5 insertions, 12 deletions
diff --git a/decoders/cjtag/pd.py b/decoders/cjtag/pd.py
index 885ecec..b6d343a 100644
--- a/decoders/cjtag/pd.py
+++ b/decoders/cjtag/pd.py
@@ -66,16 +66,9 @@ class Decoder(srd.Decoder):
outputs = ['jtag']
tags = ['Debug/trace']
channels = (
- {'id': 'tdi', 'name': 'TDI', 'desc': 'Test data input'},
- {'id': 'tdo', 'name': 'TDO', 'desc': 'Test data output'},
{'id': 'tck', 'name': 'TCK', 'desc': 'Test clock'},
{'id': 'tms', 'name': 'TMS', 'desc': 'Test mode select'},
)
- optional_channels = (
- {'id': 'trst', 'name': 'TRST#', 'desc': 'Test reset'},
- {'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'},
- {'id': 'rtck', 'name': 'RTCK', 'desc': 'Return clock signal'},
- )
annotations = tuple([tuple([s.lower(), s]) for s in jtag_states]) + ( \
('bit-tdi', 'Bit (TDI)'),
('bit-tdo', 'Bit (TDO)'),
@@ -210,7 +203,7 @@ class Decoder(srd.Decoder):
elif self.state == 'UPDATE-IR':
self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
- def handle_rising_tck_edge(self, tdi, tdo, tck, tms, trst, srst, rtck):
+ def handle_rising_tck_edge(self, tdi, tdo, tck, tms):
# Rising TCK edges always advance the state machine.
self.advance_state_machine(tms)
@@ -302,7 +295,7 @@ class Decoder(srd.Decoder):
while True:
# Wait for a rising edge on TCK.
- (tdi, tdo, tck, tms, trst, srst, rtck) = self.wait({2: 'r'})
+ tck, tms = self.wait({0: 'r'})
self.handle_tapc_state(tck, tms)
if self.cjtagstate == 'OSCAN1':
@@ -314,13 +307,13 @@ class Decoder(srd.Decoder):
self.oscan1cycle = 2
elif self.oscan1cycle == 2: # TDO
tdo_real = tms
- self.handle_rising_tck_edge(tdi_real, tdo_real, tck, tms_real, trst, srst, rtck)
+ self.handle_rising_tck_edge(tdi_real, tdo_real, tck, tms_real)
self.oscan1cycle = 0
else:
- self.handle_rising_tck_edge(tdi, tdo, tck, tms, trst, srst, rtck)
+ self.handle_rising_tck_edge(None, None, tck, tms)
while (tck == 1):
- (tdi, tdo, tck, tms_n, trst, srst, rtck) = self.wait([{2: 'f'}, {3: 'e'}])
+ tck, tms_n = self.wait([{0: 'f'}, {1: 'e'}])
if tms_n != tms:
tms = tms_n
self.handle_tms_edge(tck, tms)