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| author | Gerhard Sittig <gerhard.sittig@gmx.net> | 2017-03-14 15:33:07 +0100 |
|---|---|---|
| committer | Gerhard Sittig <gerhard.sittig@gmx.net> | 2017-03-14 19:26:09 +0100 |
| commit | cf60d0bc17b1a8e316ab5ef054f07a5fa59d1585 (patch) | |
| tree | 410c237ea5c180019d093ee9c1cbe2e1a4a46fdc /decoders | |
| parent | 04383ea876df72b7bd5c19854c30c81abdc0aa0c (diff) | |
| download | libsigrokdecode-cf60d0bc17b1a8e316ab5ef054f07a5fa59d1585.tar.gz libsigrokdecode-cf60d0bc17b1a8e316ab5ef054f07a5fa59d1585.zip | |
uart: Remove an obsolete unused routine
Diffstat (limited to 'decoders')
| -rw-r--r-- | decoders/uart/pd.py | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py index e767699..070a2f4 100644 --- a/decoders/uart/pd.py +++ b/decoders/uart/pd.py @@ -199,12 +199,6 @@ class Decoder(srd.Decoder): return True return False - def reached_bit_last(self, rxtx, bitnum): - bitpos = self.frame_start[rxtx] + ((bitnum + 1) * self.bit_width) - if self.samplenum >= bitpos: - return True - return False - def wait_for_start_bit(self, rxtx, old_signal, signal): # The start bit is always 0 (low). As the idle UART (and the stop bit) # level is 1 (high), the beginning of a start bit is a falling edge. |