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authorUwe Hermann <uwe@hermann-uwe.de>2020-01-10 21:35:00 +0100
committerUwe Hermann <uwe@hermann-uwe.de>2020-01-10 21:48:18 +0100
commitc81a365e0e81482c601371f9be8a47a048a0aae0 (patch)
tree49f0df2a39c24677d5fcaa24685f509c81a42a2d /decoders
parent32eae3386b49b6d03c6f424517d21b0c64ce9b35 (diff)
downloadlibsigrokdecode-c81a365e0e81482c601371f9be8a47a048a0aae0.tar.gz
libsigrokdecode-c81a365e0e81482c601371f9be8a47a048a0aae0.zip
sda2506: Use SrdIntEnum for pins.
Diffstat (limited to 'decoders')
-rw-r--r--decoders/sda2506/pd.py7
1 files changed, 5 insertions, 2 deletions
diff --git a/decoders/sda2506/pd.py b/decoders/sda2506/pd.py
index 5b071d8..6df5755 100644
--- a/decoders/sda2506/pd.py
+++ b/decoders/sda2506/pd.py
@@ -19,6 +19,9 @@
import re
import sigrokdecode as srd
+from common.srdhelper import SrdIntEnum
+
+Pin = SrdIntEnum.from_str('Pin', 'CLK DATA CE')
ann_cmdbit, ann_databit, ann_cmd, ann_data, ann_warning = range(5)
@@ -88,8 +91,8 @@ class Decoder(srd.Decoder):
def decode(self):
while True:
- # Wait for CLK edge or CE edge.
- clk, d, ce = self.wait([{0: 'e'}, {2: 'e'}])
+ # Wait for CLK edge or CE# edge.
+ clk, d, ce = self.wait([{Pin.CLK: 'e'}, {Pin.CE: 'e'}])
if self.matched[0] and ce == 1 and clk == 1:
# Rising clk edge and command mode.