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| author | Gerhard Sittig <gerhard.sittig@gmx.net> | 2020-07-22 22:05:54 +0200 |
|---|---|---|
| committer | Gerhard Sittig <gerhard.sittig@gmx.net> | 2020-07-26 14:38:18 +0200 |
| commit | bd7efe23c7a2e6c6698a3652fc0ce0a0d5dab156 (patch) | |
| tree | 8e8d135761c6d40239b06dd4b952e36ca242a950 /decoders | |
| parent | b0edaeb30d16af16ddbe112fe12960697196b581 (diff) | |
| download | libsigrokdecode-bd7efe23c7a2e6c6698a3652fc0ce0a0d5dab156.tar.gz libsigrokdecode-bd7efe23c7a2e6c6698a3652fc0ce0a0d5dab156.zip | |
can: avoid assignment to .id field during frame inspection
The CAN frame's ID field gets stored in an .id member, which is
unfortunate. Use .ident instead. The 'id' identifier is a Python
language word, though it's used for PD boilerplate as well. Assume
that the boilerplate is worth keeping, and harder to adjust (more
dependencies), so adjust this PD's implementation to resolve the
ambiguity.
Diffstat (limited to 'decoders')
| -rw-r--r-- | decoders/can/pd.py | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/decoders/can/pd.py b/decoders/can/pd.py index 4551896..bf8e10a 100644 --- a/decoders/can/pd.py +++ b/decoders/can/pd.py @@ -349,7 +349,7 @@ class Decoder(srd.Decoder): self.putb([4, ['Extended Identifier: %s' % s, 'Extended ID: %s' % s, 'Extended ID', 'EID']]) - self.fullid = self.id << 18 | self.eid + self.fullid = self.ident << 18 | self.eid s = '%d (0x%x)' % (self.fullid, self.fullid) self.putb([5, ['Full Identifier: %s' % s, 'Full ID: %s' % s, 'Full ID', 'FID']]) @@ -474,12 +474,13 @@ class Decoder(srd.Decoder): elif bitnum == 11: bits = self.bits[1:] bits.reverse() - # BEWARE! Clobbers the decoder's .id field! - self.id = bitpack(bits) - self.fullid = self.id - s = '%d (0x%x)' % (self.id, self.id), + # BEWARE! Don't clobber the decoder's .id field which is + # part of its boiler plate! + self.ident = bitpack(bits) + self.fullid = self.ident + s = '%d (0x%x)' % (self.ident, self.ident), self.putb([3, ['Identifier: %s' % s, 'ID: %s' % s, 'ID']]) - if (self.id & 0x7f0) == 0x7f0: + if (self.ident & 0x7f0) == 0x7f0: self.putb([16, ['Identifier bits 10..4 must not be all recessive']]) # RTR or SRR bit, depending on frame type (gets handled later). |