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authorUwe Hermann <uwe@hermann-uwe.de>2012-01-14 15:17:33 +0100
committerUwe Hermann <uwe@hermann-uwe.de>2012-01-14 15:17:33 +0100
commita10bfc48b04de832a62a474b34b23f8f24662e9a (patch)
tree4d82f046754acc49284e3e3d07fcc126c92de07e /decoders
parentb1bb5eed4ad056f760bec83e784699dabbd72a18 (diff)
downloadlibsigrokdecode-a10bfc48b04de832a62a474b34b23f8f24662e9a.tar.gz
libsigrokdecode-a10bfc48b04de832a62a474b34b23f8f24662e9a.zip
srd: SPI: s/rxcount/bitcount/.
Diffstat (limited to 'decoders')
-rw-r--r--decoders/spi.py12
1 files changed, 6 insertions, 6 deletions
diff --git a/decoders/spi.py b/decoders/spi.py
index 6b5df80..9fb6036 100644
--- a/decoders/spi.py
+++ b/decoders/spi.py
@@ -42,7 +42,7 @@ class Decoder(srd.Decoder):
def __init__(self):
self.oldsck = 1
- self.rxcount = 0
+ self.bitcount = 0
self.rxdata = 0
self.bytesreceived = 0
@@ -68,17 +68,17 @@ class Decoder(srd.Decoder):
continue
# If this is the first bit, save timestamp.
- if self.rxcount == 0:
+ if self.bitcount == 0:
self.time = samplenum
# Receive bit into our shift register.
if sdata == 1:
- self.rxdata |= 1 << (7 - self.rxcount)
+ self.rxdata |= 1 << (7 - self.bitcount)
- self.rxcount += 1
+ self.bitcount += 1
# Continue to receive if not a byte yet.
- if self.rxcount != 8:
+ if self.bitcount != 8:
continue
# self.put(0, 0, self.out_proto, out_proto) # TODO
@@ -86,7 +86,7 @@ class Decoder(srd.Decoder):
# Reset decoder state.
self.rxdata = 0
- self.rxcount = 0
+ self.bitcount = 0
# Keep stats for summary.
self.bytesreceived += 1