Rename 'probe' to 'channel' everywhere.

Variables of type 'struct srd_channel *' are consistently named 'pdch' to
make them easily distinguishable from libsigrok's 'struct sr_channel *'
variables that are consistently named 'ch'.

24 files changed, 43 insertions, 43 deletions

diff --git a/decoders/can/pd.py b/decoders/can/pd.py
index af8168c..bcc4361 100644
--- a/decoders/can/pd.py
+++ b/decoders/can/pd.py
@@ -29,7 +29,7 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['can']
-    probes = (
+    channels = (
         {'id': 'can_rx', 'name': 'CAN RX', 'desc': 'CAN bus line'},
     )
     options = (
diff --git a/decoders/dcf77/pd.py b/decoders/dcf77/pd.py
index 7cc85f6..69783c6 100644
--- a/decoders/dcf77/pd.py
+++ b/decoders/dcf77/pd.py
@@ -34,7 +34,7 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['dcf77']
-    probes = (
+    channels = (
         {'id': 'data', 'name': 'DATA', 'desc': 'DATA line'},
     )
     annotations = (
diff --git a/decoders/edid/test/test.conf b/decoders/edid/test/test.conf
index aff116c..2f3eb4c 100644
--- a/decoders/edid/test/test.conf
+++ b/decoders/edid/test/test.conf
@@ -1,5 +1,5 @@
 test tv
-	protocol-decoder i2c probe scl=0 probe sda=1
+	protocol-decoder i2c channel scl=0 channel sda=1
 	protocol-decoder edid
 	stack i2c edid
 	input i2c/edid/samsung_le46b620r3p.sr
diff --git a/decoders/guess_bitrate/__init__.py b/decoders/guess_bitrate/__init__.py
index 86f9466..9c7e6a4 100644
--- a/decoders/guess_bitrate/__init__.py
+++ b/decoders/guess_bitrate/__init__.py
@@ -20,7 +20,7 @@
 
 '''
 This protocol decoder tries to guess the bitrate / baudrate of the
-communication on the specified probe. Typically this will be used to
+communication on the specified channel. Typically this will be used to
 guess / detect the baudrate used in a UART communication snippet, but it
 could also be used to guess bitrates of certain other protocols or buses.
 
@@ -29,9 +29,9 @@ and that there are various cases in practice where the detection of the
 bitrate or baudrate will not necessarily have the expected result.
 
 The precision of the estimated bitrate / baudrate will also depend on the
-samplerate used to sample the respective probe. For good results it is
+samplerate used to sample the respective channel. For good results it is
 recommended to use a logic analyzer samplerate that is much higher than
-the expected bitrate/baudrate that might be used on the probe.
+the expected bitrate/baudrate that might be used on the channel.
 '''
 
 from .pd import *
diff --git a/decoders/guess_bitrate/pd.py b/decoders/guess_bitrate/pd.py
index 84cf6a1..d2d7c39 100644
--- a/decoders/guess_bitrate/pd.py
+++ b/decoders/guess_bitrate/pd.py
@@ -29,7 +29,7 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['guess_bitrate']
-    probes = (
+    channels = (
         {'id': 'data', 'name': 'Data', 'desc': 'Data line'},
     )
     annotations = (
diff --git a/decoders/i2c/pd.py b/decoders/i2c/pd.py
index 1770838..6bf12b9 100644
--- a/decoders/i2c/pd.py
+++ b/decoders/i2c/pd.py
@@ -72,7 +72,7 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['i2c']
-    probes = (
+    channels = (
         {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'},
         {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'},
     )
diff --git a/decoders/i2c/test/test.conf b/decoders/i2c/test/test.conf
index 880f360..bd1068b 100644
--- a/decoders/i2c/test/test.conf
+++ b/decoders/i2c/test/test.conf
@@ -1,5 +1,5 @@
 test rtc
-	protocol-decoder i2c probe scl=0 probe sda=1
+	protocol-decoder i2c channel scl=0 channel sda=1
 	input i2c/rtc_dallas_ds1307/rtc_ds1307_200khz.sr
 	output i2c annotation class data-read match rtc_ds1307_200khz_data_read.output
 	output i2c annotation class data-write match rtc_ds1307_200khz_data_write.output
@@ -7,13 +7,13 @@ test rtc
 	output i2c python match rtc_ds1307_200khz.python
 
 test motherboard
-	protocol-decoder i2c probe scl=0 probe sda=3
+	protocol-decoder i2c channel scl=0 channel sda=3
 	input i2c/gigabyte_6vle-vxl_i2c/gigabyte_6vle_vxl_i2c.sr
 	output i2c annotation match gigabyte_6vle_vxl_i2c.output
 	output i2c python match gigabyte_6vle_vxl_i2c.python
 
 test xfp
-	protocol-decoder i2c probe scl=0 probe sda=1
+	protocol-decoder i2c channel scl=0 channel sda=1
 	input i2c/network-transceivers/xfp.sr
 	output i2c binary class data-read match xfp_data_read.binary
 	output i2c binary class data-write match xfp_data_write.binary
diff --git a/decoders/i2s/pd.py b/decoders/i2s/pd.py
index af2af41..eb6a560 100644
--- a/decoders/i2s/pd.py
+++ b/decoders/i2s/pd.py
@@ -42,7 +42,7 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['i2s']
-    probes = (
+    channels = (
         {'id': 'sck', 'name': 'SCK', 'desc': 'Bit clock line'},
         {'id': 'ws', 'name': 'WS', 'desc': 'Word select line'},
         {'id': 'sd', 'name': 'SD', 'desc': 'Serial data line'},
diff --git a/decoders/ir_nec/pd.py b/decoders/ir_nec/pd.py
index b01af9e..53246dd 100644
--- a/decoders/ir_nec/pd.py
+++ b/decoders/ir_nec/pd.py
@@ -30,7 +30,7 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['ir_nec']
-    probes = (
+    channels = (
         {'id': 'ir', 'name': 'IR', 'desc': 'Data line'},
     )
     options = (
diff --git a/decoders/ir_rc5/pd.py b/decoders/ir_rc5/pd.py
index dddf937..1962459 100644
--- a/decoders/ir_rc5/pd.py
+++ b/decoders/ir_rc5/pd.py
@@ -30,7 +30,7 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['ir_rc5']
-    probes = (
+    channels = (
         {'id': 'ir', 'name': 'IR', 'desc': 'IR data line'},
     )
     options = (
diff --git a/decoders/jtag/pd.py b/decoders/jtag/pd.py
index fec75d6..21bd44b 100644
--- a/decoders/jtag/pd.py
+++ b/decoders/jtag/pd.py
@@ -62,13 +62,13 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['jtag']
-    probes = (
+    channels = (
         {'id': 'tdi',  'name': 'TDI',  'desc': 'Test data input'},
         {'id': 'tdo',  'name': 'TDO',  'desc': 'Test data output'},
         {'id': 'tck',  'name': 'TCK',  'desc': 'Test clock'},
         {'id': 'tms',  'name': 'TMS',  'desc': 'Test mode select'},
     )
-    optional_probes = (
+    optional_channels = (
         {'id': 'trst', 'name': 'TRST#', 'desc': 'Test reset'},
         {'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'},
         {'id': 'rtck', 'name': 'RTCK',  'desc': 'Return clock signal'},
@@ -200,7 +200,7 @@ class Decoder(srd.Decoder):
             self.oldpins = pins
 
             # Get individual pin values into local variables.
-            # Unused probes will have a value of > 1.
+            # Unused channels will have a value of > 1.
             (tdi, tdo, tck, tms, trst, srst, rtck) = pins
 
             # We only care about TCK edges (either rising or falling).
diff --git a/decoders/lpc/pd.py b/decoders/lpc/pd.py
index 2a12710..2ca6be1 100644
--- a/decoders/lpc/pd.py
+++ b/decoders/lpc/pd.py
@@ -104,7 +104,7 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['lpc']
-    probes = (
+    channels = (
         {'id': 'lframe', 'name': 'LFRAME#', 'desc': 'Frame'},
         {'id': 'lclk',   'name': 'LCLK',    'desc': 'Clock'},
         {'id': 'lad0',   'name': 'LAD[0]',  'desc': 'Addr/control/data 0'},
@@ -112,7 +112,7 @@ class Decoder(srd.Decoder):
         {'id': 'lad2',   'name': 'LAD[2]',  'desc': 'Addr/control/data 2'},
         {'id': 'lad3',   'name': 'LAD[3]',  'desc': 'Addr/control/data 3'},
     )
-    optional_probes = (
+    optional_channels = (
         {'id': 'lreset', 'name': 'LRESET#', 'desc': 'Reset'},
         {'id': 'ldrq',   'name': 'LDRQ#',   'desc': 'Encoded DMA / bus master request'},
         {'id': 'serirq', 'name': 'SERIRQ',  'desc': 'Serialized IRQ'},
diff --git a/decoders/mx25lxx05d/test/test.conf b/decoders/mx25lxx05d/test/test.conf
index 20162fd..0541903 100644
--- a/decoders/mx25lxx05d/test/test.conf
+++ b/decoders/mx25lxx05d/test/test.conf
@@ -1,5 +1,5 @@
 test probe
-	protocol-decoder spi probe cs=0 probe miso=1 probe clk=2 probe mosi=3
+	protocol-decoder spi channel cs=0 channel miso=1 channel clk=2 channel mosi=3
 	protocol-decoder mx25lxx05d
 	stack spi mx25lxx05d
 	input spi/mx25l1605d/mx25l1605d_probe.sr
diff --git a/decoders/onewire_link/__init__.py b/decoders/onewire_link/__init__.py
index 5bd6c55..d153f93 100644
--- a/decoders/onewire_link/__init__.py
+++ b/decoders/onewire_link/__init__.py
@@ -37,7 +37,7 @@ overdrive communication speed. The following minimal values should be used:
  - overdrive available: 2MHz minimum, 5MHz suggested
  - overdrive not available: 400kHz minimum, 1MHz suggested
 
-Probes:
+Channels:
 1-Wire requires a single signal, but some master implementations might have a
 separate signal used to deliver power to the bus during temperature conversion
 as an example. This power signal is currently not used.
diff --git a/decoders/onewire_link/pd.py b/decoders/onewire_link/pd.py
index ceb5da2..aa1cb2e 100644
--- a/decoders/onewire_link/pd.py
+++ b/decoders/onewire_link/pd.py
@@ -29,10 +29,10 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['onewire_link']
-    probes = (
+    channels = (
         {'id': 'owr', 'name': 'OWR', 'desc': '1-Wire signal line'},
     )
-    optional_probes = (
+    optional_channels = (
         {'id': 'pwr', 'name': 'PWR', 'desc': '1-Wire power supply pin'},
     )
     options = (
diff --git a/decoders/parallel/__init__.py b/decoders/parallel/__init__.py
index ea55077..cc1f3d1 100644
--- a/decoders/parallel/__init__.py
+++ b/decoders/parallel/__init__.py
@@ -20,14 +20,14 @@
 
 '''
 This protocol decoder can decode synchronous parallel buses with various
-number of data bits/probes and one (optional) clock line.
+number of data bits/channels and one (optional) clock line.
 
 If no clock line is supplied, the decoder works slightly differently in
-that it interprets every transition on any of the supplied data probes
+that it interprets every transition on any of the supplied data channels
 like there had been a clock transition.
 
-It is required to use the lowest data probes, and use consecutive ones.
-For example, for a 4-bit sync parallel bus, probes D0/D1/D2/D3 (and CLK)
+It is required to use the lowest data channels, and use consecutive ones.
+For example, for a 4-bit sync parallel bus, channels D0/D1/D2/D3 (and CLK)
 should be used. Using combinations like D7/D12/D3/D15 is not supported.
 For an 8-bit bus you should use D0-D7, for a 16-bit bus use D0-D15 and so on.
 '''
diff --git a/decoders/parallel/pd.py b/decoders/parallel/pd.py
index 330d514..094b12a 100644
--- a/decoders/parallel/pd.py
+++ b/decoders/parallel/pd.py
@@ -54,9 +54,9 @@ Packet:
    word <worditemcount> is 7, and so on.
 '''
 
-def probe_list(num_probes):
+def channel_list(num_channels):
     l = [{'id': 'clk', 'name': 'CLK', 'desc': 'Clock line'}]
-    for i in range(num_probes):
+    for i in range(num_channels):
         d = {'id': 'd%d' % i, 'name': 'D%d' % i, 'desc': 'Data line %d' % i}
         l.append(d)
     return tuple(l)
@@ -70,7 +70,7 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['parallel']
-    optional_probes = probe_list(8)
+    optional_channels = channel_list(8)
     options = (
         {'id': 'clock_edge', 'desc': 'Clock edge to sample on',
             'default': 'rising', 'values': ('rising', 'falling')},
diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py
index 7d84b3d..b1a8704 100644
--- a/decoders/spi/pd.py
+++ b/decoders/spi/pd.py
@@ -31,7 +31,7 @@ Commands:
  - 'DATA': <data1> contains the MISO data, <data2> contains the MOSI data.
    The data is _usually_ 8 bits (but can also be fewer or more bits).
    Both data items are Python numbers (not strings), or None if the respective
-   probe was not supplied.
+   channel was not supplied.
  - 'BITS': <data1>/<data2> contain a list of bit values in this MISO/MOSI data
    item, and for each of those also their respective start-/endsample numbers.
  - 'CS CHANGE': <data1> is the old CS# pin value, <data2> is the new value.
@@ -69,10 +69,10 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['spi']
-    probes = (
+    channels = (
         {'id': 'clk', 'name': 'CLK', 'desc': 'Clock'},
     )
-    optional_probes = (
+    optional_channels = (
         {'id': 'miso', 'name': 'MISO', 'desc': 'Master in, slave out'},
         {'id': 'mosi', 'name': 'MOSI', 'desc': 'Master out, slave in'},
         {'id': 'cs', 'name': 'CS#', 'desc': 'Chip-select'},
diff --git a/decoders/spi/test/test.conf b/decoders/spi/test/test.conf
index d5531b1..e08b788 100644
--- a/decoders/spi/test/test.conf
+++ b/decoders/spi/test/test.conf
@@ -1,11 +1,11 @@
 test atmega32_00
-	protocol-decoder spi probe cs=0 probe mosi=1 probe clk=2
+	protocol-decoder spi channel cs=0 channel mosi=1 channel clk=2
 	input spi/spi_atmega32/spi_atmega32_00.sr
 	output spi annotation class mosi-data match atmega32_00_mosi.output
 	output spi annotation class miso-data match atmega32_00_miso.output
 
 test mx25l1605d_probe
-	protocol-decoder spi probe cs=0 probe miso=1 probe clk=2 probe mosi=3
+	protocol-decoder spi channel cs=0 channel miso=1 channel clk=2 channel mosi=3
 	input spi/mx25l1605d/mx25l1605d_probe.sr
 	output spi annotation class mosi-data match mx25l1605d_probe_mosi.output
 	output spi annotation class miso-data match mx25l1605d_probe_miso.output
diff --git a/decoders/tlc5620/pd.py b/decoders/tlc5620/pd.py
index 6fedf5d..7961154 100644
--- a/decoders/tlc5620/pd.py
+++ b/decoders/tlc5620/pd.py
@@ -36,11 +36,11 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['tlc5620']
-    probes = (
+    channels = (
         {'id': 'clk', 'name': 'CLK', 'desc': 'Serial interface clock'},
         {'id': 'data', 'name': 'DATA', 'desc': 'Serial interface data'},
     )
-    optional_probes = (
+    optional_channels = (
         {'id': 'load', 'name': 'LOAD', 'desc': 'Serial interface load control'},
         {'id': 'ldac', 'name': 'LDAC', 'desc': 'Load DAC'},
     )
diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py
index 6119b8e..57031d7 100644
--- a/decoders/uart/pd.py
+++ b/decoders/uart/pd.py
@@ -78,7 +78,7 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['uart']
-    optional_probes = (
+    optional_channels = (
         # Allow specifying only one of the signals, e.g. if only one data
         # direction exists (or is relevant).
         {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'},
diff --git a/decoders/uart/test/test.conf b/decoders/uart/test/test.conf
index b5f0f0d..f15b04b 100644
--- a/decoders/uart/test/test.conf
+++ b/decoders/uart/test/test.conf
@@ -1,5 +1,5 @@
 test trekstor_ebr30_a
-	protocol-decoder uart probe rx=1
+	protocol-decoder uart channel rx=1
 	input uart/trekstor_ebr30_a/trekstor_ebr30_a_uart.sr
 	output uart annotation class rx-data match trekstor_rx.output
 	output uart annotation class tx-data match trekstor_tx.output
diff --git a/decoders/usb_signalling/pd.py b/decoders/usb_signalling/pd.py
index deecf1a..e63817e 100644
--- a/decoders/usb_signalling/pd.py
+++ b/decoders/usb_signalling/pd.py
@@ -82,7 +82,7 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['usb_signalling']
-    probes = (
+    channels = (
         {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
         {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
     )
diff --git a/decoders/z80/pd.py b/decoders/z80/pd.py
index f6bafb1..299a20e 100644
--- a/decoders/z80/pd.py
+++ b/decoders/z80/pd.py
@@ -56,7 +56,7 @@ ann_data_cycle_map = {
 
 def reduce_bus(bus):
     if 0xFF in bus:
-        return None # unassigned bus probes
+        return None # unassigned bus channels
     else:
         return reduce(lambda a, b: (a << 1) | b, reversed(bus))
 
@@ -72,7 +72,7 @@ class Decoder(srd.Decoder):
     license  = 'gplv3+'
     inputs   = ['logic']
     outputs  = ['z80']
-    probes = tuple({
+    channels = tuple({
             'id': 'd%d' % i,
             'name': 'D%d' % i,
             'desc': 'Data bus line %d' % i
@@ -82,7 +82,7 @@ class Decoder(srd.Decoder):
         {'id': 'rd', 'name': '/RD', 'desc': 'Memory or I/O read'},
         {'id': 'wr', 'name': '/WR', 'desc': 'Memory or I/O write'},
     )
-    optional_probes = (
+    optional_channels = (
         {'id': 'mreq', 'name': '/MREQ', 'desc': 'Memory request'},
         {'id': 'iorq', 'name': '/IORQ', 'desc': 'I/O request'},
     ) + tuple({