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| author | Daniel Elstner <daniel.kitta@gmail.com> | 2014-02-28 21:10:53 +0100 |
|---|---|---|
| committer | Daniel Elstner <daniel.kitta@gmail.com> | 2014-02-28 21:16:24 +0100 |
| commit | 3831aa891c7a9822a376023419a1fea1a698463c (patch) | |
| tree | 7798d2c291103c7c2cd56a4e4a66ddc60f9ae7cd /decoders | |
| parent | 739f9313539c559949748d918e59865496ad8f6e (diff) | |
| download | libsigrokdecode-3831aa891c7a9822a376023419a1fea1a698463c.tar.gz libsigrokdecode-3831aa891c7a9822a376023419a1fea1a698463c.zip | |
z80: Display not-taken conditional calls correctly.
Diffstat (limited to 'decoders')
| -rw-r--r-- | decoders/z80/pd.py | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/decoders/z80/pd.py b/decoders/z80/pd.py index 8fadff5..4663f95 100644 --- a/decoders/z80/pd.py +++ b/decoders/z80/pd.py @@ -291,9 +291,9 @@ class Decoder(srd.Decoder): if self.want_imm > 0: return OpState.IMM1 self.ann_dasm = Ann.INSTR - if self.want_read > 0: + if self.want_read > 0 and self.prev_cycle in (Cycle.MEMRD, Cycle.IORD): return OpState.ROP1 - if self.want_write > 0: + if self.want_write > 0 and self.prev_cycle in (Cycle.MEMWR, Cycle.IOWR): return OpState.WOP1 return OpState.RESTART @@ -302,18 +302,18 @@ class Decoder(srd.Decoder): if self.want_imm > 1: return OpState.IMM2 self.ann_dasm = Ann.INSTR - if self.want_read > 0: + if self.want_read > 0 and self.prev_cycle in (Cycle.MEMRD, Cycle.IORD): return OpState.ROP1 - if self.want_write > 0: + if self.want_write > 0 and self.prev_cycle in (Cycle.MEMWR, Cycle.IOWR): return OpState.WOP1 return OpState.RESTART def on_state_IMM2(self): self.arg_imm |= self.pend_data << 8 self.ann_dasm = Ann.INSTR - if self.want_read > 0: + if self.want_read > 0 and self.prev_cycle in (Cycle.MEMRD, Cycle.IORD): return OpState.ROP1 - if self.want_write > 0: + if self.want_write > 0 and self.prev_cycle in (Cycle.MEMWR, Cycle.IOWR): return OpState.WOP1 return OpState.RESTART @@ -334,7 +334,7 @@ class Decoder(srd.Decoder): self.arg_read |= self.pend_data << 8 self.mnemonic = '{ro:04X}' self.ann_dasm = Ann.ROP - if self.want_write > 0: + if self.want_write > 0 and self.prev_cycle in (Cycle.MEMWR, Cycle.IOWR): return OpState.WOP1 return OpState.RESTART |