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| author | Soeren Apel <soeren@apelpie.net> | 2020-06-21 12:10:59 +0200 |
|---|---|---|
| committer | Soeren Apel <soeren@apelpie.net> | 2021-02-13 23:21:10 +0100 |
| commit | 114adb4997b71e93267e3816710c8b019ae927c0 (patch) | |
| tree | 9c9b51fe5188db63f7311a2dc6f4516909b42270 /decoders | |
| parent | b8c8dc8a649ad0a76bccbfae7198cc9c8cb2ccda (diff) | |
| download | libsigrokdecode-114adb4997b71e93267e3816710c8b019ae927c0.tar.gz libsigrokdecode-114adb4997b71e93267e3816710c8b019ae927c0.zip | |
Implement basic flushing
Diffstat (limited to 'decoders')
| -rw-r--r-- | decoders/pca9571/pd.py | 8 | ||||
| -rw-r--r-- | decoders/tca6408a/pd.py | 6 |
2 files changed, 7 insertions, 7 deletions
diff --git a/decoders/pca9571/pd.py b/decoders/pca9571/pd.py index a878142..ea8715d 100644 --- a/decoders/pca9571/pd.py +++ b/decoders/pca9571/pd.py @@ -62,8 +62,8 @@ class Decoder(srd.Decoder): self.out_ann = self.register(srd.OUTPUT_ANN) self.out_logic = self.register(srd.OUTPUT_LOGIC) -# def flush(self): -# self.put_logic_states() + def flush(self): + self.put_logic_states() def putx(self, data): self.put(self.ss, self.es, self.out_ann, data) @@ -82,7 +82,7 @@ class Decoder(srd.Decoder): '(%02X) are different' % self.last_write]]) else: operation = ['Outputs set', 'W'] -# self.put_logic_states() + self.put_logic_states() self.last_write = b self.putx([1, [operation[0] + ': %02X' % b, @@ -99,8 +99,6 @@ class Decoder(srd.Decoder): cmd, databyte = data self.ss, self.es = ss, es - self.put_logic_states() - # State machine. if cmd in ('ACK', 'BITS'): # Discard 'ACK' and 'BITS'. pass diff --git a/decoders/tca6408a/pd.py b/decoders/tca6408a/pd.py index 0d63cc3..4ca1082 100644 --- a/decoders/tca6408a/pd.py +++ b/decoders/tca6408a/pd.py @@ -64,6 +64,9 @@ class Decoder(srd.Decoder): self.out_ann = self.register(srd.OUTPUT_ANN) self.out_logic = self.register(srd.OUTPUT_LOGIC) + def flush(self): + self.put_logic_states() + def putx(self, data): self.put(self.ss, self.es, self.out_ann, data) @@ -78,6 +81,7 @@ class Decoder(srd.Decoder): # TODO def handle_reg_0x01(self, b): + self.put_logic_states() self.putx([1, ['Outputs set: %02X' % b]]) self.logic_value = b @@ -109,8 +113,6 @@ class Decoder(srd.Decoder): # Store the start/end samples of this I²C packet. self.ss, self.es = ss, es - self.put_logic_states() - # State machine. if self.state == 'IDLE': # Wait for an I²C START condition. |