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| author | Gerhard Sittig <gerhard.sittig@gmx.net> | 2017-06-18 15:51:35 +0200 |
|---|---|---|
| committer | Gerhard Sittig <gerhard.sittig@gmx.net> | 2017-06-20 23:10:14 +0200 |
| commit | c240da484645ab78b19c8a8e2938df67039660f0 (patch) | |
| tree | db2eac21e1b6a3f47881fda2ce46ffaa9e244d3f /decoders/usb_signalling | |
| parent | 73dc48310c47f4e3ebb6ee6de67983603ddd3ea3 (diff) | |
| download | libsigrokdecode-c240da484645ab78b19c8a8e2938df67039660f0.tar.gz libsigrokdecode-c240da484645ab78b19c8a8e2938df67039660f0.zip | |
usb_signalling: Move another edge detection to common backend code
Rephrase how the 'WAIT IDLE' stage skips over all-low input signals.
Have the next high level on either line detected in common code.
Diffstat (limited to 'decoders/usb_signalling')
| -rw-r--r-- | decoders/usb_signalling/pd.py | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/decoders/usb_signalling/pd.py b/decoders/usb_signalling/pd.py index c0e0141..ae0f651 100644 --- a/decoders/usb_signalling/pd.py +++ b/decoders/usb_signalling/pd.py @@ -329,9 +329,10 @@ class Decoder(srd.Decoder): elif self.state == 'GET EOP': self.get_eop(sym) elif self.state == 'WAIT IDLE': + # Skip "all-low" input. Wait for high level on either DP or DM. pins = self.wait({'skip': 1}) - if pins == (0, 0): - continue + while not pins[0] and not pins[1]: + pins = self.wait([{0: 'h'}, {1: 'h'}]) if self.samplenum - self.samplenum_lastedge > 1: sym = symbols[self.options['signalling']][pins] self.handle_idle(sym) |