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author | Uwe Hermann <uwe@hermann-uwe.de> | 2013-09-11 19:20:15 +0200 |
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committer | Uwe Hermann <uwe@hermann-uwe.de> | 2013-09-12 15:56:05 +0200 |
commit | 83be7b8384e0dc20b84de831e5922fb9c6d0762d (patch) | |
tree | 29ce3ab669442554a9c0b1bef2f25b1912ed2a1a /decoders/uart | |
parent | 15ac66048e7dcd9c6a0ddbfc5cab2e56f95b3f56 (diff) | |
download | libsigrokdecode-83be7b8384e0dc20b84de831e5922fb9c6d0762d.tar.gz libsigrokdecode-83be7b8384e0dc20b84de831e5922fb9c6d0762d.zip |
uart: Fix corner-case that can occur with LA triggers.
Assume that the initial pin state is 1/high for the RX and TX lines.
This fixes the decode when an LA triggers on e.g. TX=low (the first
sample would be low in that case, so the falling edge for the start bit
would be missed by the decoder).
Diffstat (limited to 'decoders/uart')
-rw-r--r-- | decoders/uart/pd.py | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py index b10012a..cca8952 100644 --- a/decoders/uart/pd.py +++ b/decoders/uart/pd.py @@ -111,8 +111,8 @@ class Decoder(srd.Decoder): self.stopbit1 = [-1, -1] self.startsample = [-1, -1] self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT'] - self.oldbit = [None, None] - self.oldpins = None + self.oldbit = [1, 1] + self.oldpins = [1, 1] def start(self, metadata): self.samplerate = metadata['samplerate'] @@ -268,14 +268,6 @@ class Decoder(srd.Decoder): # continue self.oldpins, (rx, tx) = pins, pins - # First sample: Save RX/TX value. - if self.oldbit[RX] == None: - self.oldbit[RX] = rx - continue - if self.oldbit[TX] == None: - self.oldbit[TX] = tx - continue - # State machine. for rxtx in (RX, TX): signal = rx if (rxtx == RX) else tx |