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authorUwe Hermann <uwe@hermann-uwe.de>2013-09-08 15:16:11 +0200
committerUwe Hermann <uwe@hermann-uwe.de>2013-09-08 15:16:11 +0200
commit95097f3108033f69c19a315a7d042383b7295628 (patch)
tree1d480eab8a277e1b0c6562a9176d754ef3992c13 /decoders/uart/pd.py
parentb055603b3ff59be1497b96a1a22da262b8753d75 (diff)
downloadlibsigrokdecode-95097f3108033f69c19a315a7d042383b7295628.tar.gz
libsigrokdecode-95097f3108033f69c19a315a7d042383b7295628.zip
i2c: Fix corner-case that can occur with LA triggers.
Until now the I2C PD was basically ignoring the very first sample, and using that as the initial 'oldscl'/'oldsda' value. However, if your logic analyzers trigger on, say, SDA=low that will result in a file where the first sample is really important since it is the one which the PD will need to know that there's a falling edge on SDA. Thus, assume both SCL and SDA are high/1 when the PD starts. This is a good assumption since both pins have pullups on them in practice and are thus high/1 when the bus is idle. Later on we might want to have config options to let the PD assume other states of SDA/SCL initially.
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