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author | Gerhard Sittig <gerhard.sittig@gmx.net> | 2017-12-22 15:16:27 +0100 |
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committer | Uwe Hermann <uwe@hermann-uwe.de> | 2018-01-01 22:15:51 +0100 |
commit | ca24954fa8c82919446eec8114e4007f0b024797 (patch) | |
tree | 7d6097e657d5a5fbc2098405be79c983539c6811 /decoders/tca6408a | |
parent | a0b7e07f5576605141e543f9d81a220a920edc27 (diff) | |
download | libsigrokdecode-ca24954fa8c82919446eec8114e4007f0b024797.tar.gz libsigrokdecode-ca24954fa8c82919446eec8114e4007f0b024797.zip |
parallel: unbreak and improve "word" de-multiplexing
The previous implementation prepared but never fully enabled the
accumulation of several multi-bit items into words that span multiple
bus cycles (think: address or data de-multiplexing on memory busses).
Complete the accumulation, and fixup the end samplenumber for word
annotations. Fixup the endianess logic (the condition was inverted).
Rephrase calculation to be more Python idiomatic.
Default to word size zero, and only emit word annotations for non-zero
word size specs. This keeps the implementation backwards compatible and
still passes the test suite. Default behaviour is most appropriate for
interactive use in GUI environments, while automated processing will
find consistent behaviour across all setups (non-multiplexed busses, and
multiplexed busses with "words" that span one or multiple cycles).
Diffstat (limited to 'decoders/tca6408a')
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