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| author | Soeren Apel <soeren@apelpie.net> | 2020-06-26 20:16:15 +0200 |
|---|---|---|
| committer | Soeren Apel <soeren@apelpie.net> | 2021-02-13 23:19:06 +0100 |
| commit | b8c8dc8a649ad0a76bccbfae7198cc9c8cb2ccda (patch) | |
| tree | 6bab9eeaf2240c9c1423aa6d84bac8cc9afdd3bf /decoders/tca6408a | |
| parent | 9b6c0354ce4bab15c524928f2c0059f1df543ad9 (diff) | |
| download | libsigrokdecode-b8c8dc8a649ad0a76bccbfae7198cc9c8cb2ccda.tar.gz libsigrokdecode-b8c8dc8a649ad0a76bccbfae7198cc9c8cb2ccda.zip | |
Rename logic_class to logic_group and output as group-wise RLE
Diffstat (limited to 'decoders/tca6408a')
| -rw-r--r-- | decoders/tca6408a/pd.py | 18 |
1 files changed, 7 insertions, 11 deletions
diff --git a/decoders/tca6408a/pd.py b/decoders/tca6408a/pd.py index 01c4e6d..0d63cc3 100644 --- a/decoders/tca6408a/pd.py +++ b/decoders/tca6408a/pd.py @@ -57,10 +57,8 @@ class Decoder(srd.Decoder): self.state = 'IDLE' self.chip = -1 - self.logic_es = 1 - self.logic_data = [] - for i in range(NUM_OUTPUT_CHANNELS): - self.logic_data.append(bytes([1])) + self.logic_output_es = 0 + self.logic_value = 0 def start(self): self.out_ann = self.register(srd.OUTPUT_ANN) @@ -70,10 +68,10 @@ class Decoder(srd.Decoder): self.put(self.ss, self.es, self.out_ann, data) def put_logic_states(self): - if (self.es > self.logic_es): - for i in range(NUM_OUTPUT_CHANNELS): - self.put(self.logic_es, self.es, self.out_logic, [i, self.logic_data[i]]) - self.logic_es = self.es + if (self.es > self.logic_output_es): + data = bytes([self.logic_value]) + self.put(self.logic_output_es, self.es, self.out_logic, [0, data]) + self.logic_output_es = self.es def handle_reg_0x00(self, b): self.putx([1, ['State of inputs: %02X' % b]]) @@ -81,9 +79,7 @@ class Decoder(srd.Decoder): def handle_reg_0x01(self, b): self.putx([1, ['Outputs set: %02X' % b]]) - for i in range(NUM_OUTPUT_CHANNELS): - bit = (b & (1 << i)) != 0 - self.logic_data[i] = bytes([bit]) + self.logic_value = b def handle_reg_0x02(self, b): self.putx([1, ['Polarity inverted: %02X' % b]]) |