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| author | Bert Vermeulen <bert@biot.com> | 2012-02-01 00:13:42 +0100 |
|---|---|---|
| committer | Bert Vermeulen <bert@biot.com> | 2012-02-01 00:13:42 +0100 |
| commit | b77614bc977475102062ac5d1c8fe8e55349315a (patch) | |
| tree | 36845bc97277429b1cc5b863ad3e4aaa92a85097 /decoders/spi | |
| parent | dcdf48838748df02bc3028c4a26ea6d4506ee542 (diff) | |
| download | libsigrokdecode-b77614bc977475102062ac5d1c8fe8e55349315a.tar.gz libsigrokdecode-b77614bc977475102062ac5d1c8fe8e55349315a.zip | |
srd: rename extra_probes to optional_probes in all PDs
Diffstat (limited to 'decoders/spi')
| -rw-r--r-- | decoders/spi/spi.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/decoders/spi/spi.py b/decoders/spi/spi.py index a06498b..ff186dd 100644 --- a/decoders/spi/spi.py +++ b/decoders/spi/spi.py @@ -66,7 +66,7 @@ class Decoder(srd.Decoder): {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'}, {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'}, ] - extra_probes = [] # TODO + optional_probes = [] # TODO options = { 'cs_polarity': ['CS# polarity', ACTIVE_LOW], 'cpol': ['Clock polarity', CPOL_0], |