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| author | Gerhard Sittig <gerhard.sittig@gmx.net> | 2017-06-18 13:50:48 +0200 |
|---|---|---|
| committer | Gerhard Sittig <gerhard.sittig@gmx.net> | 2017-06-20 23:10:09 +0200 |
| commit | 73dc48310c47f4e3ebb6ee6de67983603ddd3ea3 (patch) | |
| tree | 7e2c54c5fdfa7a0eed98793051bdbdfa8dc39178 /decoders/rtc8564/__init__.py | |
| parent | eff37627aa217defa784337c4f4aa309477311fc (diff) | |
| download | libsigrokdecode-73dc48310c47f4e3ebb6ee6de67983603ddd3ea3.tar.gz libsigrokdecode-73dc48310c47f4e3ebb6ee6de67983603ddd3ea3.zip | |
pwm: Fixup sample numbers for binary output
Do reference the period's start and end sample numbers when the
duty cycle is written to the binary output stream. The previous
implementation inappropriately used the period counter instead.
Diffstat (limited to 'decoders/rtc8564/__init__.py')
0 files changed, 0 insertions, 0 deletions