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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2014-01-13 23:26:36 +0100 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2014-01-13 23:26:36 +0100 |
| commit | 8eafa2613d2541e934a04874cd35cbc944c3168b (patch) | |
| tree | 635eef0f5ba77bb1df1423f64be9c16d9abd0b5e /decoders/parallel/__init__.py | |
| parent | 6af04d5a36a47b11dcf10bb629105600aa5a66eb (diff) | |
| download | libsigrokdecode-8eafa2613d2541e934a04874cd35cbc944c3168b.tar.gz libsigrokdecode-8eafa2613d2541e934a04874cd35cbc944c3168b.zip | |
parallel: Make CLK probe optional.
When no CLK probe is supplied to this PD, handle any transition on
any of the supplied data probes as if there had been a CLK transition.
(based on a suggestion/patch by "bmx" from the #sigrok channel, thanks!)
Diffstat (limited to 'decoders/parallel/__init__.py')
| -rw-r--r-- | decoders/parallel/__init__.py | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/decoders/parallel/__init__.py b/decoders/parallel/__init__.py index a338c43..ea55077 100644 --- a/decoders/parallel/__init__.py +++ b/decoders/parallel/__init__.py @@ -20,7 +20,11 @@ ''' This protocol decoder can decode synchronous parallel buses with various -number of data bits/probes and one clock line. +number of data bits/probes and one (optional) clock line. + +If no clock line is supplied, the decoder works slightly differently in +that it interprets every transition on any of the supplied data probes +like there had been a clock transition. It is required to use the lowest data probes, and use consecutive ones. For example, for a 4-bit sync parallel bus, probes D0/D1/D2/D3 (and CLK) |