From 8eafa2613d2541e934a04874cd35cbc944c3168b Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Mon, 13 Jan 2014 23:26:36 +0100 Subject: parallel: Make CLK probe optional. When no CLK probe is supplied to this PD, handle any transition on any of the supplied data probes as if there had been a CLK transition. (based on a suggestion/patch by "bmx" from the #sigrok channel, thanks!) --- decoders/parallel/__init__.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'decoders/parallel/__init__.py') diff --git a/decoders/parallel/__init__.py b/decoders/parallel/__init__.py index a338c43..ea55077 100644 --- a/decoders/parallel/__init__.py +++ b/decoders/parallel/__init__.py @@ -20,7 +20,11 @@ ''' This protocol decoder can decode synchronous parallel buses with various -number of data bits/probes and one clock line. +number of data bits/probes and one (optional) clock line. + +If no clock line is supplied, the decoder works slightly differently in +that it interprets every transition on any of the supplied data probes +like there had been a clock transition. It is required to use the lowest data probes, and use consecutive ones. For example, for a 4-bit sync parallel bus, probes D0/D1/D2/D3 (and CLK) -- cgit v1.2.3-70-g09d2