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| author | Daniel Thompson <daniel@redfelineninja.org.uk> | 2016-01-22 08:29:09 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2016-01-29 00:14:57 +0100 |
| commit | 96a044da40fd33e6f3273f0052fdd12f54770150 (patch) | |
| tree | 6ad28cbc8efcf0ebd4fa1f8d346ac7ad71e8d96d /decoders/onewire_network/__init__.py | |
| parent | 27c69645218c7cc88c991c8c18b585ffd092acc0 (diff) | |
| download | libsigrokdecode-96a044da40fd33e6f3273f0052fdd12f54770150.tar.gz libsigrokdecode-96a044da40fd33e6f3273f0052fdd12f54770150.zip | |
uart: Optimize handling of samples when tx and rx are both idle
Re-enable the fast path for identical samples but only when both
pins are waiting for the start bit. For sparse data sets (I tested
UT61E capture log) the optimization results in a >4x decode
improvement.
Diffstat (limited to 'decoders/onewire_network/__init__.py')
0 files changed, 0 insertions, 0 deletions