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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2012-05-18 21:42:29 +0200 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2012-05-18 21:42:29 +0200 |
| commit | cd287c56af4e005e36faa26a88f6ef6dcbb2c902 (patch) | |
| tree | be1f14acc4c2db1c0fd556ee32dd0c151744749f /decoders/mx25lxx05d | |
| parent | 7cfbf663d2acd5c1d289e1eb6f4aafbf76dc169d (diff) | |
| download | libsigrokdecode-cd287c56af4e005e36faa26a88f6ef6dcbb2c902.tar.gz libsigrokdecode-cd287c56af4e005e36faa26a88f6ef6dcbb2c902.zip | |
srd: MX25Lxx05D: Fix inverted SRWD bit handling.
Diffstat (limited to 'decoders/mx25lxx05d')
| -rw-r--r-- | decoders/mx25lxx05d/mx25lxx05d.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/decoders/mx25lxx05d/mx25lxx05d.py b/decoders/mx25lxx05d/mx25lxx05d.py index a5dab2e..1d41fd4 100644 --- a/decoders/mx25lxx05d/mx25lxx05d.py +++ b/decoders/mx25lxx05d/mx25lxx05d.py @@ -113,7 +113,7 @@ def decode_status_reg(data): ret += 'Device is %sin continuously program mode (CP mode).\n' % s # Bits[7:7]: SRWD (status register write disable) - s = '' if (data & (1 << 7)) else 'not ' + s = 'not ' if (data & (1 << 7)) else '' ret += 'Status register writes are %sallowed.\n' % s return ret |