diff options
author | Uwe Hermann <uwe@hermann-uwe.de> | 2019-07-31 21:40:07 +0200 |
---|---|---|
committer | Uwe Hermann <uwe@hermann-uwe.de> | 2019-08-06 20:42:49 +0200 |
commit | 739b654a10c34065c021f0bb1152e3a47c8b3b7d (patch) | |
tree | 66bc901895df0c00064526302661060824ff360e /decoders/mrf24j40/pd.py | |
parent | e64a9722829b78cc9e0c1089307ed76cdadad1fe (diff) | |
download | libsigrokdecode-739b654a10c34065c021f0bb1152e3a47c8b3b7d.tar.gz libsigrokdecode-739b654a10c34065c021f0bb1152e3a47c8b3b7d.zip |
mrf24j40: Add RX/TX frame annotations.
Diffstat (limited to 'decoders/mrf24j40/pd.py')
-rw-r--r-- | decoders/mrf24j40/pd.py | 35 |
1 files changed, 33 insertions, 2 deletions
diff --git a/decoders/mrf24j40/pd.py b/decoders/mrf24j40/pd.py index b242ee6..58d3dfd 100644 --- a/decoders/mrf24j40/pd.py +++ b/decoders/mrf24j40/pd.py @@ -20,6 +20,8 @@ import sigrokdecode as srd from .lists import * +TX, RX = range(2) + class Decoder(srd.Decoder): api_version = 3 id = 'mrf24j40' @@ -36,11 +38,15 @@ class Decoder(srd.Decoder): ('lread', 'Long register read commands'), ('lwrite', 'Long register write commands'), ('warning', 'Warnings'), + ('tx-frame', 'TX frame'), + ('rx-frame', 'RX frame'), ) annotation_rows = ( ('read', 'Read', (0, 2)), ('write', 'Write', (1, 3)), ('warnings', 'Warnings', (4,)), + ('tx-frames', 'TX frames', (5,)), + ('rx-frames', 'RX frames', (6,)), ) def __init__(self): @@ -48,8 +54,9 @@ class Decoder(srd.Decoder): def reset(self): self.ss_cmd, self.es_cmd = 0, 0 - self.mosi_bytes = [] - self.miso_bytes = [] + self.ss_frame, self.es_frame = [0, 0], [0, 0] + self.mosi_bytes, self.miso_bytes = [], [] + self.framecache = [[], []] def start(self): self.out_ann = self.register(srd.OUTPUT_ANN) @@ -68,6 +75,20 @@ class Decoder(srd.Decoder): write = self.mosi_bytes[0] & 0x1 reg = (self.mosi_bytes[0] >> 1) & 0x3f reg_desc = sregs.get(reg, 'illegal') + for rxtx in (RX, TX): + if self.framecache[rxtx] == []: + continue + bit0 = self.mosi_bytes[1] & (1 << 0) + if rxtx == TX and not (reg_desc == 'TXNCON' and bit0 == 1): + continue + if rxtx == RX and not (reg_desc == 'RXFLUSH' and bit0 == 1): + continue + idx = 5 if rxtx == TX else 6 + xmitdir = 'TX' if rxtx == TX else 'RX' + frame = ' '.join(['%02X' % b for b in self.framecache[rxtx]]) + self.put(self.ss_frame[rxtx], self.es_frame[rxtx], self.out_ann, + [idx, ['%s frame: %s' % (xmitdir, frame)]]) + self.framecache[rxtx] = [] if write: self.putx([1, ['%s: %#x' % (reg_desc, self.mosi_bytes[1])]]) else: @@ -99,6 +120,16 @@ class Decoder(srd.Decoder): else: self.putx([2, ['%s: %#x' % (reg_desc, self.miso_bytes[2])]]) + for rxtx in (RX, TX): + if rxtx == RX and reg_desc[:3] != 'RX:': + continue + if rxtx == TX and reg_desc[:3] != 'TX:': + continue + if len(self.framecache[rxtx]) == 0: + self.ss_frame[rxtx] = self.ss_cmd + self.es_frame[rxtx] = self.es_cmd + self.framecache[rxtx] += [self.mosi_bytes[2]] if rxtx == TX else [self.miso_bytes[2]] + def decode(self, ss, es, data): ptype = data[0] if ptype == 'CS-CHANGE': |