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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2015-12-23 20:01:48 +0100 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2015-12-24 02:28:55 +0100 |
| commit | 2f37032807e19bc93b7f3223e1568db46318790c (patch) | |
| tree | 937b0b0d24112203fd14f2f6124567f5f81cf25f /decoders/jitter | |
| parent | 2824e81140d3a8e37464f758cf67f50f2f7afca7 (diff) | |
| download | libsigrokdecode-2f37032807e19bc93b7f3223e1568db46318790c.tar.gz libsigrokdecode-2f37032807e19bc93b7f3223e1568db46318790c.zip | |
Use self.out_binary naming consistently across all PDs.
Diffstat (limited to 'decoders/jitter')
| -rw-r--r-- | decoders/jitter/pd.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/decoders/jitter/pd.py b/decoders/jitter/pd.py index d40c643..ba1bffa 100644 --- a/decoders/jitter/pd.py +++ b/decoders/jitter/pd.py @@ -77,7 +77,7 @@ class Decoder(srd.Decoder): self.clk_edge = edge_detector[self.options['clk_polarity']] self.sig_edge = edge_detector[self.options['sig_polarity']] self.out_ann = self.register(srd.OUTPUT_ANN) - self.out_bin = self.register(srd.OUTPUT_BINARY) + self.out_binary = self.register(srd.OUTPUT_BINARY) self.out_clk_missed = self.register(srd.OUTPUT_META, meta=(int, 'Clock missed', 'Clock transition missed')) self.out_sig_missed = self.register(srd.OUTPUT_META, @@ -111,7 +111,7 @@ class Decoder(srd.Decoder): return # Format the delta to an ASCII float value terminated by a newline. x = str(delta) + '\n' - self.put(self.clk_start, self.sig_start, self.out_bin, + self.put(self.clk_start, self.sig_start, self.out_binary, [0, x.encode('UTF-8')]) # Helper function for missed clock and signal annotations. |