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authorVesa-Pekka Palmu <vpalmu@depili.fi>2022-12-26 19:18:36 +0200
committerGerhard Sittig <gerhard.sittig@gmx.net>2023-01-09 20:11:44 +0100
commitadb8233a0bf30b1d9ee9176e1caa5dc8ae1830dd (patch)
tree8b4bdc252e5187e63d8dc0a717e232e3e5c45579 /decoders/ieee488/pd.py
parentf534ce442c271c13af5d216e16f56322dc586822 (diff)
downloadlibsigrokdecode-adb8233a0bf30b1d9ee9176e1caa5dc8ae1830dd.tar.gz
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adf435x: Move decoder logic to SPI transfers
The previous implementation of the ADF435x decoder assumed knowledge of internal details which are the SPI transport layer's responsibility. And encoded an inappropriate chip select polarity in the process (falling CS edge). The datasheet specifies that previously clocked in data bits get latched on rising LE edges. Not all setups were affected, that's why the issue went unnoticed before. Use the lower layer's TRANSFER annotation to process the completion of an ADF435x register access, after BITS annotations made the location of individual bits available. The LE (CS) signal's polarity remains a detail of the SPI decoding layer, and must be configured there. The SPI decoder's default matches the ADF435x chip's expectation. This fixes bug #1814. Reported-by: Martin Homuth-Rosemann <homuth-rosemann@gmx.net>
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