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authorUwe Hermann <uwe@hermann-uwe.de>2013-09-08 15:16:11 +0200
committerUwe Hermann <uwe@hermann-uwe.de>2013-09-08 15:16:11 +0200
commit95097f3108033f69c19a315a7d042383b7295628 (patch)
tree1d480eab8a277e1b0c6562a9176d754ef3992c13 /decoders/i2c
parentb055603b3ff59be1497b96a1a22da262b8753d75 (diff)
downloadlibsigrokdecode-95097f3108033f69c19a315a7d042383b7295628.tar.gz
libsigrokdecode-95097f3108033f69c19a315a7d042383b7295628.zip
i2c: Fix corner-case that can occur with LA triggers.
Until now the I2C PD was basically ignoring the very first sample, and using that as the initial 'oldscl'/'oldsda' value. However, if your logic analyzers trigger on, say, SDA=low that will result in a file where the first sample is really important since it is the one which the PD will need to know that there's a falling edge on SDA. Thus, assume both SCL and SDA are high/1 when the PD starts. This is a good assumption since both pins have pullups on them in practice and are thus high/1 when the bus is idle. Later on we might want to have config options to let the PD assume other states of SDA/SCL initially.
Diffstat (limited to 'decoders/i2c')
-rw-r--r--decoders/i2c/pd.py12
1 files changed, 3 insertions, 9 deletions
diff --git a/decoders/i2c/pd.py b/decoders/i2c/pd.py
index 0b85c66..c2eb524 100644
--- a/decoders/i2c/pd.py
+++ b/decoders/i2c/pd.py
@@ -86,9 +86,9 @@ class Decoder(srd.Decoder):
self.wr = -1
self.is_repeat_start = 0
self.state = 'FIND START'
- self.oldscl = None
- self.oldsda = None
- self.oldpins = None
+ self.oldscl = 1
+ self.oldsda = 1
+ self.oldpins = (1, 1)
def start(self, metadata):
self.out_proto = self.add(srd.OUTPUT_PROTO, 'i2c')
@@ -206,12 +206,6 @@ class Decoder(srd.Decoder):
continue
self.oldpins, (scl, sda) = pins, pins
- # First sample: Save SCL/SDA value.
- if self.oldscl == None:
- self.oldscl = scl
- self.oldsda = sda
- continue
-
# TODO: Wait until the bus is idle (SDA = SCL = 1) first?
# State machine.