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authorGerhard Sittig <gerhard.sittig@gmx.net>2023-07-17 18:51:02 +0200
committerGerhard Sittig <gerhard.sittig@gmx.net>2023-07-18 21:28:44 +0200
commit35753ccad522da1a1241beec0736aa7049a290bb (patch)
treeeb8cfc1dbf49b960e4700477d9591bb27449b0bd /decoders/i2c
parente7c6af6eb047bb751c53741f18353e8d1635d8d5 (diff)
downloadlibsigrokdecode-35753ccad522da1a1241beec0736aa7049a290bb.tar.gz
libsigrokdecode-35753ccad522da1a1241beec0736aa7049a290bb.zip
i2c: also shift first address byte for 10bit slave addresses
The first address byte in an I2C transfer always carries the R/W bit. Always shift this byte regardless of 7/10 bit addresses, and always emit separate annotations for the address value part and the R/W bit part.
Diffstat (limited to 'decoders/i2c')
-rw-r--r--decoders/i2c/pd.py7
1 files changed, 3 insertions, 4 deletions
diff --git a/decoders/i2c/pd.py b/decoders/i2c/pd.py
index a2558dd..a6c7437 100644
--- a/decoders/i2c/pd.py
+++ b/decoders/i2c/pd.py
@@ -198,11 +198,10 @@ class Decoder(srd.Decoder):
self.rem_addr_bytes = 1
self.slave_addr_7 = addr_byte >> 1
self.slave_addr_10 = None
- is_seven = self.slave_addr_7 is not None
+ has_rw_bit = self.is_write is None
if self.is_write is None:
read_bit = bool(addr_byte & 1)
- shift_seven = self.options['address_format'] == 'shifted'
- if is_seven and shift_seven:
+ if self.options['address_format'] == 'shifted':
d = d >> 1
self.is_write = False if read_bit else True
else:
@@ -240,7 +239,7 @@ class Decoder(srd.Decoder):
texts = [t.format(b = bit_value) for t in texts]
self.putg(ss_bit, es_bit, cls, texts)
- if cmd.startswith('ADDRESS') and is_seven:
+ if cmd.startswith('ADDRESS') and has_rw_bit:
# Assign the last bit's location to the R/W annotation.
# Adjust the address value's location to the left.
ss_bit, es_bit = self.data_bits[-1][1], self.data_bits[-1][2]