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authorGerhard Sittig <gerhard.sittig@gmx.net>2017-06-18 15:51:35 +0200
committerGerhard Sittig <gerhard.sittig@gmx.net>2017-06-20 23:10:14 +0200
commitc240da484645ab78b19c8a8e2938df67039660f0 (patch)
treedb2eac21e1b6a3f47881fda2ce46ffaa9e244d3f /decoders/guess_bitrate/pd.py
parent73dc48310c47f4e3ebb6ee6de67983603ddd3ea3 (diff)
downloadlibsigrokdecode-c240da484645ab78b19c8a8e2938df67039660f0.tar.gz
libsigrokdecode-c240da484645ab78b19c8a8e2938df67039660f0.zip
usb_signalling: Move another edge detection to common backend code
Rephrase how the 'WAIT IDLE' stage skips over all-low input signals. Have the next high level on either line detected in common code.
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