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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2014-08-16 21:03:00 +0200 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2014-08-16 21:37:21 +0200 |
| commit | 903e9b14c84400579e0d786b7a96e9e587b5849b (patch) | |
| tree | 36f797411831bd33e54bff95402ca3635fd3cf1f /decoders/ds1307 | |
| parent | 37834eed4b104fcf77258cca846302911dea34ca (diff) | |
| download | libsigrokdecode-903e9b14c84400579e0d786b7a96e9e587b5849b.tar.gz libsigrokdecode-903e9b14c84400579e0d786b7a96e9e587b5849b.zip | |
ds1307: Handle SRAM register accesses.
Diffstat (limited to 'decoders/ds1307')
| -rw-r--r-- | decoders/ds1307/pd.py | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/decoders/ds1307/pd.py b/decoders/ds1307/pd.py index d718c93..2447af5 100644 --- a/decoders/ds1307/pd.py +++ b/decoders/ds1307/pd.py @@ -171,6 +171,10 @@ class Decoder(srd.Decoder): 'Square wave rate: %s' % r, 'SQW rate: %s' % r, 'Rate: %s' % r, 'RS: %s' % s, 'RS', 'R']]) + def handle_reg_0x3f(self, b): # RAM (bytes 0x08-0x3f) + self.putd(7, 0, [8, ['RAM', 'R']]) + self.putd(7, 0, [23, ['SRAM: 0x%02X' % b, '0x%02X' % b]]) + def decode(self, ss, es, data): cmd, databyte = data @@ -209,7 +213,8 @@ class Decoder(srd.Decoder): return # Otherwise: Get data bytes until a STOP condition occurs. if cmd == 'DATA WRITE': - handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg) + r = self.reg if self.reg < 8 else 0x3f + handle_reg = getattr(self, 'handle_reg_0x%02x' % r) handle_reg(databyte) self.reg += 1 # TODO: Check for NACK! @@ -233,7 +238,8 @@ class Decoder(srd.Decoder): pass # TODO elif self.state == 'READ RTC REGS2': if cmd == 'DATA READ': - handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg) + r = self.reg if self.reg < 8 else 0x3f + handle_reg = getattr(self, 'handle_reg_0x%02x' % r) handle_reg(databyte) self.reg += 1 # TODO: Check for NACK! |