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| author | Gerhard Sittig <gerhard.sittig@gmx.net> | 2020-11-07 14:47:21 +0100 |
|---|---|---|
| committer | Gerhard Sittig <gerhard.sittig@gmx.net> | 2020-11-11 19:31:47 +0100 |
| commit | e2317ec49b8b04c7f8b3358c2e9c264de4280539 (patch) | |
| tree | bde678ecc8ce98679d8086799a3fa1eb42019d3f /decoders/common/srdhelper/mod.py | |
| parent | 615f86f6bf7f7166f2975c9efe7e727bf2b65734 (diff) | |
| download | libsigrokdecode-e2317ec49b8b04c7f8b3358c2e9c264de4280539.tar.gz libsigrokdecode-e2317ec49b8b04c7f8b3358c2e9c264de4280539.zip | |
parallel: add option to sample data on either clock edge
Add 'either' as another choice in addition to rising and falling clock
edge. This is useful since parallel busses exist which communicate at
double data rate (DDR).
Unobfuscate the mapping between displayed option text and .wait()
condition codes while we are here.
Diffstat (limited to 'decoders/common/srdhelper/mod.py')
0 files changed, 0 insertions, 0 deletions