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| author | Weixiao Zhang <waveletboy@gmail.com> | 2018-11-20 21:41:45 -0600 |
|---|---|---|
| committer | Weixiao Zhang <waveletboy@gmail.com> | 2018-11-20 21:41:45 -0600 |
| commit | c78c8f6faf51eb5fa66dd2ca94439b40ad1047b0 (patch) | |
| tree | ab22361864c8966df09b38f9aef9c73bbfe99c29 /decoders/avr_isp/__init__.py | |
| parent | 2eb6af30c323a8e3f692f1030f2726b661745f6d (diff) | |
| download | libsigrokdecode-c78c8f6faf51eb5fa66dd2ca94439b40ad1047b0.tar.gz libsigrokdecode-c78c8f6faf51eb5fa66dd2ca94439b40ad1047b0.zip | |
i2s: Fix 2 issues.
1. WS = 0, Left Channel; WS = 1, Right Channel
2. Data start and end at falling edge of SCK
Diffstat (limited to 'decoders/avr_isp/__init__.py')
0 files changed, 0 insertions, 0 deletions