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authorGerhard Sittig <gerhard.sittig@gmx.net>2019-12-21 17:02:50 +0100
committerUwe Hermann <uwe@hermann-uwe.de>2020-01-04 22:35:38 +0100
commit4370348c4fcdbd708715c35a38fdf06c9364d518 (patch)
tree4e66d4bb05fdde2c5828a9af8ddea12e16ec1368 /decoders/avr_isp/__init__.py
parentf4314037f6cc646c92575c6555d3ed6e51c14b29 (diff)
downloadlibsigrokdecode-4370348c4fcdbd708715c35a38fdf06c9364d518.tar.gz
libsigrokdecode-4370348c4fcdbd708715c35a38fdf06c9364d518.zip
ps2: end data byte at rising clock edge of the stop bit
Data byte transmission is complete when the STOP bit was communicated. End the STOP bit at the rising CLOCK edge of the 11th bit time, do not rely on the host's clock inhibit after data transmission. This avoids the unexpected expansion of a STOP bit well into the next data byte. This fixes bug #1460, where absence of host activity after the first data byte loses synchronization to the input stream. Rephrase pin level sampling while we are here. Reflect that the clock line is used for .wait() conditions, but its level is not evaluated. Only data line levels get processed. Comment on the implementation's assumption of specific input data (the device as transmitter, host transmit may not be supported, or can result in unexpected output). Which may be acceptable yet maintainers need to remain aware.
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