pjdl: support PAD bit adjacent to last HIGH DATA bit (no LOW)

The PJDL decoder's previous implementation was incomplete. It assumed
that PAD bits always start with a rising edge. Which made the decoder
miss the next byte when a previous byte's MSB is set, and the last DATA
bit and the next PAD bit kept the signal HIGH between them (no LOW phase
was seen between these symbols).

Keep the check for the LOW level after the byte's last DATA bit within
the bit times' tolerance. But accept when the level remains HIGH, and
check for the HIGH bit's width starting from the end of the last DATA
bit. Also start the PAD bit's annotation from that "virtual" edge.

This patch is based on a fix that was
Submitted-By: Julio Aguirre <jcallano@gmail.com>

0 files changed, 0 insertions, 0 deletions