diff options
author | Gerhard Sittig <gerhard.sittig@gmx.net> | 2017-12-22 13:55:45 +0100 |
---|---|---|
committer | Uwe Hermann <uwe@hermann-uwe.de> | 2018-01-01 22:15:51 +0100 |
commit | b0ac80e2f0a147ddaeab525604d8b0cacf0fd6cd (patch) | |
tree | 13a5412633b575ed8011a5dbda9f8a843e965c30 | |
parent | f30fdbb692c00d2dc2b9199384d17a49e886a7c9 (diff) | |
download | libsigrokdecode-b0ac80e2f0a147ddaeab525604d8b0cacf0fd6cd.tar.gz libsigrokdecode-b0ac80e2f0a147ddaeab525604d8b0cacf0fd6cd.zip |
parallel: unify decode() code paths with and without clock signal
Instead of implementing two main loops for operation in the presence and
in the absence of a clock line, use a common main loop which operates on
pre-determined wait conditions.
-rw-r--r-- | decoders/parallel/pd.py | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/decoders/parallel/pd.py b/decoders/parallel/pd.py index 140b7b8..4c09d86 100644 --- a/decoders/parallel/pd.py +++ b/decoders/parallel/pd.py @@ -176,10 +176,11 @@ class Decoder(srd.Decoder): for i in range(1, len(self.optional_channels)): if self.has_channel(i): conds.append({i: 'e'}) - while True: - self.handle_bits(self.wait(conds)[1:]) else: # Sample on the rising or falling CLK edge (depends on config). - while True: - pins = self.wait({0: self.options['clock_edge'][0]}) - self.handle_bits(pins[1:]) + edge = self.options['clock_edge'][0] + conds = [{0: edge}] + + while True: + pins = self.wait(conds) + self.handle_bits(pins[1:]) |