diff options
| author | Uwe Hermann <uwe@hermann-uwe.de> | 2020-04-10 20:58:26 +0200 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2020-04-11 01:13:59 +0200 |
| commit | 93ddf98bfaa47033cf4ce2dbb369cef168e8a0df (patch) | |
| tree | f47a490ddaa7cd529b0b43bf345a08921a933de7 | |
| parent | 7b0f3c78c5cda82b900937f3be2e08b063b84f3c (diff) | |
| download | libsigrokdecode-93ddf98bfaa47033cf4ce2dbb369cef168e8a0df.tar.gz libsigrokdecode-93ddf98bfaa47033cf4ce2dbb369cef168e8a0df.zip | |
adxl345: Use SrdIntEnum for the state machine.
| -rw-r--r-- | decoders/adxl345/pd.py | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/decoders/adxl345/pd.py b/decoders/adxl345/pd.py index 8b23147..8ca995b 100644 --- a/decoders/adxl345/pd.py +++ b/decoders/adxl345/pd.py @@ -60,6 +60,8 @@ class Bit(): Ann = SrdIntEnum.from_str('Ann', 'READ WRITE MB REG_ADDRESS REG_DATA WARNING') +St = SrdIntEnum.from_str('St', 'IDLE ADDRESS_BYTE DATA') + class Decoder(srd.Decoder): api_version = 3 id = 'adxl345' @@ -92,7 +94,7 @@ class Decoder(srd.Decoder): self.operation = None self.address = 0 self.data = -1 - self.state = 'IDLE' + self.state = St.IDLE self.ss, self.es = -1, -1 self.samples_per_bit = 0 @@ -376,9 +378,9 @@ class Decoder(srd.Decoder): cs_old, cs_new = data[1:] if cs_old is not None and cs_old == 1 and cs_new == 0: self.ss, self.es = ss, es - self.state = 'ADDRESS-BYTE' + self.state = St.ADDRESS_BYTE else: - self.state = 'IDLE' + self.state = St.IDLE elif ptype == 'BITS': if data[1] is not None: @@ -389,7 +391,7 @@ class Decoder(srd.Decoder): if self.mosi is None and self.miso is None: return - if self.state == 'ADDRESS-BYTE': + if self.state == St.ADDRESS_BYTE: # OPERATION BIT op_bit = self.get_bit(Channel.MOSI) self.put(op_bit[1], op_bit[2], self.out_ann, @@ -412,9 +414,9 @@ class Decoder(srd.Decoder): [Ann.REG_ADDRESS, ['ADDRESS: 0x%02X' % self.address, 'ADDR: 0x%02X' % self.address, '0x%02X' % self.address]]) self.ss = -1 - self.state = 'DATA' + self.state = St.DATA - elif self.state == 'DATA': + elif self.state == St.DATA: self.reg.extend(self.mosi if self.operation == Operation.WRITE else self.miso) self.mosi, self.miso = [], [] |