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| author | Stephan Thiele <stephan.thiele@mailbox.org> | 2019-02-22 19:29:53 +0100 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2019-09-13 15:19:33 +0200 |
| commit | 741dba7858f41c555d01d041c8481bf9ef155e7d (patch) | |
| tree | 73ed9ed6cdd11b3265c981804b3e0f91a54a1316 | |
| parent | 7f75d50706245e64b6d5675b60fce4b5f957283f (diff) | |
| download | libsigrokdecode-741dba7858f41c555d01d041c8481bf9ef155e7d.tar.gz libsigrokdecode-741dba7858f41c555d01d041c8481bf9ef155e7d.zip | |
can: display CRC type + correct decoding of CRC-17
| -rw-r--r-- | decoders/can/pd.py | 36 |
1 files changed, 26 insertions, 10 deletions
diff --git a/decoders/can/pd.py b/decoders/can/pd.py index ff4c78a..2d346bb 100644 --- a/decoders/can/pd.py +++ b/decoders/can/pd.py @@ -162,41 +162,57 @@ class Decoder(srd.Decoder): if bitnum == (self.last_databit + 1): self.ss_block = self.samplenum - # CRC sequence (15 bits) - elif bitnum == (self.last_databit + 15): + if self.fd: + if self.dlc < 16: + self.crc_len = 27 # 17 + SBC + stuff bits + else: + self.crc_len = 21 + else: + self.crc_len = 15 + + # CRC sequence (15 bits, 17 bits or 21 bits) + elif bitnum == (self.last_databit + self.crc_len): + if self.fd: + if self.dlc < 16: + crc_type = "CRC-17" + else: + crc_type = "CRC-21" + else: + crc_type = "CRC-15" + x = self.last_databit + 1 - crc_bits = self.bits[x:x + 15 + 1] + crc_bits = self.bits[x:x + self.crc_len + 1] self.crc = int(''.join(str(d) for d in crc_bits), 2) - self.putb([11, ['CRC sequence: 0x%04x' % self.crc, - 'CRC: 0x%04x' % self.crc, 'CRC']]) + self.putb([11, ['%s sequence: 0x%04x' % (crc_type, self.crc), + '%s: 0x%04x' % (crc_type, self.crc), '%s' % crc_type]]) if not self.is_valid_crc(crc_bits): self.putb([16, ['CRC is invalid']]) # CRC delimiter bit (recessive) - elif bitnum == (self.last_databit + 16): + elif bitnum == (self.last_databit + self.crc_len + 1): self.putx([12, ['CRC delimiter: %d' % can_rx, 'CRC d: %d' % can_rx, 'CRC d']]) if can_rx != 1: self.putx([16, ['CRC delimiter must be a recessive bit']]) # ACK slot bit (dominant: ACK, recessive: NACK) - elif bitnum == (self.last_databit + 17): + elif bitnum == (self.last_databit + self.crc_len + 2): ack = 'ACK' if can_rx == 0 else 'NACK' self.putx([13, ['ACK slot: %s' % ack, 'ACK s: %s' % ack, 'ACK s']]) # ACK delimiter bit (recessive) - elif bitnum == (self.last_databit + 18): + elif bitnum == (self.last_databit + self.crc_len + 3): self.putx([14, ['ACK delimiter: %d' % can_rx, 'ACK d: %d' % can_rx, 'ACK d']]) if can_rx != 1: self.putx([16, ['ACK delimiter must be a recessive bit']]) # Remember start of EOF (see below). - elif bitnum == (self.last_databit + 19): + elif bitnum == (self.last_databit + self.crc_len + 4): self.ss_block = self.samplenum # End of frame (EOF), 7 recessive bits - elif bitnum == (self.last_databit + 25): + elif bitnum == (self.last_databit + self.crc_len + 11): self.putb([2, ['End of frame', 'EOF', 'E']]) if self.rawbits[-7:] != [1, 1, 1, 1, 1, 1, 1]: self.putb([16, ['End of frame (EOF) must be 7 recessive bits']]) |