srd: PDs: Use strings for states, too.

6 files changed, 64 insertions, 99 deletions

diff --git a/decoders/dcf77/dcf77.py b/decoders/dcf77/dcf77.py
index ab600ed..eabceee 100644
--- a/decoders/dcf77/dcf77.py
+++ b/decoders/dcf77/dcf77.py
@@ -23,10 +23,6 @@
 import sigrokdecode as srd
 import calendar
 
-# States
-WAIT_FOR_RISING_EDGE = 0
-GET_BIT = 1
-
 # Annotation feed formats
 ANN_ASCII = 0
 
@@ -57,7 +53,7 @@ class Decoder(srd.Decoder):
     ]
 
     def __init__(self, **kwargs):
-        self.state = WAIT_FOR_RISING_EDGE
+        self.state = 'WAIT FOR RISING EDGE'
         self.oldval = None
         self.samplenum = 0
         self.bit_start = 0
@@ -208,7 +204,7 @@ class Decoder(srd.Decoder):
 
             self.samplenum += 1 # FIXME. Use samplenum. Off-by-one?
 
-            if self.state == WAIT_FOR_RISING_EDGE:
+            if self.state == 'WAIT FOR RISING EDGE':
                 # Wait until the next rising edge occurs.
                 if not (self.oldval == 0 and val == 1):
                     self.oldval = val
@@ -262,7 +258,7 @@ class Decoder(srd.Decoder):
                     self.handle_dcf77_bit(bit)
                     self.bitcount += 1
 
-                self.state = WAIT_FOR_RISING_EDGE
+                self.state = 'WAIT FOR RISING EDGE'
 
             else:
                 raise Exception('Invalid state: %d' % self.state)
diff --git a/decoders/i2c/i2c.py b/decoders/i2c/i2c.py
index 5f952fa..2c11be0 100644
--- a/decoders/i2c/i2c.py
+++ b/decoders/i2c/i2c.py
@@ -50,12 +50,6 @@ protocol = {
     'DATA WRITE':      ['DATA WRITE',    'DW'],
 }
 
-# States
-FIND_START = 0
-FIND_ADDRESS = 1
-FIND_DATA = 2
-FIND_ACK = 3
-
 class Decoder(srd.Decoder):
     api_version = 1
     id = 'i2c'
@@ -91,7 +85,7 @@ class Decoder(srd.Decoder):
         self.databyte = 0
         self.wr = -1
         self.is_repeat_start = 0
-        self.state = FIND_START
+        self.state = 'FIND START'
         self.oldscl = None
         self.oldsda = None
 
@@ -128,7 +122,7 @@ class Decoder(srd.Decoder):
         self.put(self.out_ann, [ANN_SHIFTED, [protocol[cmd][0]]])
         self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol[cmd][1]]])
 
-        self.state = FIND_ADDRESS
+        self.state = 'FIND ADDRESS'
         self.bitcount = self.databyte = 0
         self.is_repeat_start = 1
         self.wr = -1
@@ -154,20 +148,20 @@ class Decoder(srd.Decoder):
         # read/write and ACK/NACK bits.
         self.put(self.out_ann, [ANN_RAW, ['0x%.2x' % self.databyte]])
 
-        if self.state == FIND_ADDRESS:
+        if self.state == 'FIND ADDRESS':
             # The READ/WRITE bit is only in address bytes, not data bytes.
             self.wr = 0 if (self.databyte & 1) else 1
             d = self.databyte >> 1
-        elif self.state == FIND_DATA:
+        elif self.state == 'FIND DATA':
             d = self.databyte
 
-        if self.state == FIND_ADDRESS and self.wr == 1:
+        if self.state == 'FIND ADDRESS' and self.wr == 1:
             cmd = 'ADDRESS WRITE'
-        elif self.state == FIND_ADDRESS and self.wr == 0:
+        elif self.state == 'FIND ADDRESS' and self.wr == 0:
             cmd = 'ADDRESS READ'
-        elif self.state == FIND_DATA and self.wr == 1:
+        elif self.state == 'FIND DATA' and self.wr == 1:
             cmd = 'DATA WRITE'
-        elif self.state == FIND_DATA and self.wr == 0:
+        elif self.state == 'FIND DATA' and self.wr == 0:
             cmd = 'DATA READ'
 
         self.put(self.out_proto, [cmd, d])
@@ -177,7 +171,7 @@ class Decoder(srd.Decoder):
         # Done with this packet.
         self.startsample = -1
         self.bitcount = self.databyte = 0
-        self.state = FIND_ACK
+        self.state = 'FIND ACK'
 
     def get_ack(self, scl, sda):
         self.startsample = self.samplenum
@@ -187,7 +181,7 @@ class Decoder(srd.Decoder):
         self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol[ack_bit][1]]])
         # There could be multiple data bytes in a row, so either find
         # another data byte or a STOP condition next.
-        self.state = FIND_DATA
+        self.state = 'FIND DATA'
 
     def found_stop(self, scl, sda):
         self.startsample = self.samplenum
@@ -195,7 +189,7 @@ class Decoder(srd.Decoder):
         self.put(self.out_ann, [ANN_SHIFTED, [protocol['STOP'][0]]])
         self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol['STOP'][1]]])
 
-        self.state = FIND_START
+        self.state = 'FIND START'
         self.is_repeat_start = 0
         self.wr = -1
 
@@ -216,20 +210,20 @@ class Decoder(srd.Decoder):
             # TODO: Wait until the bus is idle (SDA = SCL = 1) first?
 
             # State machine.
-            if self.state == FIND_START:
+            if self.state == 'FIND START':
                 if self.is_start_condition(scl, sda):
                     self.found_start(scl, sda)
-            elif self.state == FIND_ADDRESS:
+            elif self.state == 'FIND ADDRESS':
                 if self.is_data_bit(scl, sda):
                     self.found_address_or_data(scl, sda)
-            elif self.state == FIND_DATA:
+            elif self.state == 'FIND DATA':
                 if self.is_data_bit(scl, sda):
                     self.found_address_or_data(scl, sda)
                 elif self.is_start_condition(scl, sda):
                     self.found_start(scl, sda)
                 elif self.is_stop_condition(scl, sda):
                     self.found_stop(scl, sda)
-            elif self.state == FIND_ACK:
+            elif self.state == 'FIND ACK':
                 if self.is_data_bit(scl, sda):
                     self.get_ack(scl, sda)
             else:
diff --git a/decoders/nunchuk/nunchuk.py b/decoders/nunchuk/nunchuk.py
index 0e5e742..b91e3ea 100644
--- a/decoders/nunchuk/nunchuk.py
+++ b/decoders/nunchuk/nunchuk.py
@@ -22,13 +22,6 @@
 
 import sigrokdecode as srd
 
-# States
-IDLE = 0
-START = 1
-NUNCHUK_SLAVE = 2
-INIT = 3
-INITIALIZED = 4
-
 class Decoder(srd.Decoder):
     api_version = 1
     id = 'nunchuk'
@@ -47,7 +40,7 @@ class Decoder(srd.Decoder):
     ]
 
     def __init__(self, **kwargs):
-        self.state = IDLE # TODO: Can we assume a certain initial state?
+        self.state = 'IDLE' # TODO: Can we assume a certain initial state?
         self.sx = self.sy = self.ax = self.ay = self.az = self.bz = self.bc = 0
         self.databytecount = 0
 
@@ -63,7 +56,7 @@ class Decoder(srd.Decoder):
         cmd, databyte = data
 
         if cmd == 'START': # TODO: Handle 'Sr' here, too?
-            self.state = START
+            self.state = 'START'
 
         elif cmd == 'START REPEAT':
             pass # FIXME
@@ -80,7 +73,7 @@ class Decoder(srd.Decoder):
             else:
                 pass # TODO: What to do here? Ignore? Error?
 
-        elif cmd == 'DATA READ' and self.state == INITIALIZED:
+        elif cmd == 'DATA READ' and self.state == 'INITIALIZED':
             if self.databytecount == 0:
                 self.sx = databyte
             elif self.databytecount == 1:
@@ -114,23 +107,23 @@ class Decoder(srd.Decoder):
             # TODO: If 6 bytes read -> save and reset
 
         # TODO
-        elif cmd == 'DATA READ' and self.state != INITIALIZED:
+        elif cmd == 'DATA READ' and self.state != 'INITIALIZED':
             pass
 
         elif cmd == 'DATA WRITE':
-            if self.state == IDLE:
-                self.state = INITIALIZED
+            if self.state == 'IDLE':
+                self.state = 'INITIALIZED'
             return
 
-            if databyte == 0x40 and self.state == START:
-                self.state = INIT
-            elif databyte == 0x00 and self.state == INIT:
+            if databyte == 0x40 and self.state == 'START':
+                self.state = 'INIT'
+            elif databyte == 0x00 and self.state == 'INIT':
                 self.put(ss, es, self.out_ann, [0, ['Initialize nunchuk']])
-                self.state = INITIALIZED
+                self.state = 'INITIALIZED'
             else:
                 pass # TODO
 
         elif cmd == 'STOP':
-            self.state = INITIALIZED
+            self.state = 'INITIALIZED'
             self.databytecount = 0
 
diff --git a/decoders/rtc8564/rtc8564.py b/decoders/rtc8564/rtc8564.py
index d2838e3..2e2f10f 100644
--- a/decoders/rtc8564/rtc8564.py
+++ b/decoders/rtc8564/rtc8564.py
@@ -22,14 +22,6 @@
 
 import sigrokdecode as srd
 
-# States
-IDLE = 0
-GET_SLAVE_ADDR = 1
-GET_REG_ADDR = 2
-READ_RTC_REGS = 3
-READ_RTC_REGS2 = 4
-WRITE_RTC_REGS = 5
-
 # Return the specified BCD number (max. 8 bits) as integer.
 def bcd2int(b):
     return (b & 0x0f) + ((b >> 4) * 10)
@@ -56,7 +48,7 @@ class Decoder(srd.Decoder):
     ]
 
     def __init__(self, **kwargs):
-        self.state = IDLE
+        self.state = 'IDLE'
         self.hours = -1
         self.minutes = -1
         self.seconds = -1
@@ -160,28 +152,28 @@ class Decoder(srd.Decoder):
         self.ss, self.es = ss, es
 
         # State machine.
-        if self.state == IDLE:
+        if self.state == 'IDLE':
             # Wait for an I2C START condition.
             if cmd != 'START':
                 return
-            self.state = GET_SLAVE_ADDR
+            self.state = 'GET SLAVE ADDR'
             self.block_start_sample = ss
-        elif self.state == GET_SLAVE_ADDR:
+        elif self.state == 'GET SLAVE ADDR':
             # Wait for an address write operation.
             # TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
             if cmd != 'ADDRESS WRITE':
                 return
-            self.state = GET_REG_ADDR
-        elif self.state == GET_REG_ADDR:
+            self.state = 'GET REG ADDR'
+        elif self.state == 'GET REG ADDR':
             # Wait for a data write (master selects the slave register).
             if cmd != 'DATA WRITE':
                 return
             self.reg = databyte
-            self.state = WRITE_RTC_REGS
-        elif self.state == WRITE_RTC_REGS:
+            self.state = 'WRITE RTC REGS'
+        elif self.state == 'WRITE RTC REGS':
             # If we see a Repeated Start here, it's probably an RTC read.
             if cmd == 'START REPEAT':
-                self.state = READ_RTC_REGS
+                self.state = 'READ RTC REGS'
                 return
             # Otherwise: Get data bytes until a STOP condition occurs.
             if cmd == 'DATA WRITE':
@@ -195,18 +187,18 @@ class Decoder(srd.Decoder):
                     self.years, self.hours, self.minutes, self.seconds)
                 self.put(self.block_start_sample, es, self.out_ann,
                          [0, ['Written date/time: %s' % d]])
-                self.state = IDLE
+                self.state = 'IDLE'
             else:
                 pass # TODO
-        elif self.state == READ_RTC_REGS:
+        elif self.state == 'READ RTC REGS':
             # Wait for an address read operation.
             # TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
             if cmd == 'ADDRESS READ':
-                self.state = READ_RTC_REGS2
+                self.state = 'READ RTC REGS2'
                 return
             else:
                 pass # TODO
-        elif self.state == READ_RTC_REGS2:
+        elif self.state == 'READ RTC REGS2':
             if cmd == 'DATA READ':
                 handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
                 handle_reg(databyte)
@@ -217,7 +209,7 @@ class Decoder(srd.Decoder):
                     self.years, self.hours, self.minutes, self.seconds)
                 self.put(self.block_start_sample, es, self.out_ann,
                          [0, ['Read date/time: %s' % d]])
-                self.state = IDLE
+                self.state = 'IDLE'
             else:
                 pass # TODO?
         else:
diff --git a/decoders/uart/uart.py b/decoders/uart/uart.py
index dd9f88d..2bb61dd 100644
--- a/decoders/uart/uart.py
+++ b/decoders/uart/uart.py
@@ -22,13 +22,6 @@
 
 import sigrokdecode as srd
 
-# States
-WAIT_FOR_START_BIT = 0
-GET_START_BIT = 1
-GET_DATA_BITS = 2
-GET_PARITY_BIT = 3
-GET_STOP_BITS = 4
-
 # Used for differentiating between the two data directions.
 RX = 0
 TX = 1
@@ -111,7 +104,7 @@ class Decoder(srd.Decoder):
         self.startsample = [-1, -1]
 
         # Initial state.
-        self.state = [WAIT_FOR_START_BIT, WAIT_FOR_START_BIT]
+        self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
 
         self.oldbit = [None, None]
 
@@ -153,7 +146,7 @@ class Decoder(srd.Decoder):
         # Save the sample number where the start bit begins.
         self.frame_start[rxtx] = self.samplenum
 
-        self.state[rxtx] = GET_START_BIT
+        self.state[rxtx] = 'GET START BIT'
 
     def get_start_bit(self, rxtx, signal):
         # Skip samples until we're in the middle of the start bit.
@@ -172,7 +165,7 @@ class Decoder(srd.Decoder):
         self.databyte[rxtx] = 0
         self.startsample[rxtx] = -1
 
-        self.state[rxtx] = GET_DATA_BITS
+        self.state[rxtx] = 'GET DATA BITS'
 
         self.put(self.frame_start[rxtx], self.samplenum, self.out_proto,
                  ['STARTBIT', rxtx, self.startbit[rxtx]])
@@ -206,7 +199,7 @@ class Decoder(srd.Decoder):
             self.cur_data_bit[rxtx] += 1
             return
 
-        self.state[rxtx] = GET_PARITY_BIT
+        self.state[rxtx] = 'GET PARITY BIT'
 
         self.put(self.startsample[rxtx], self.samplenum - 1, self.out_proto,
                  ['DATA', rxtx, self.databyte[rxtx]])
@@ -224,7 +217,7 @@ class Decoder(srd.Decoder):
     def get_parity_bit(self, rxtx, signal):
         # If no parity is used/configured, skip to the next state immediately.
         if self.options['parity_type'] == 'none':
-            self.state[rxtx] = GET_STOP_BITS
+            self.state[rxtx] = 'GET STOP BITS'
             return
 
         # Skip samples until we're in the middle of the parity bit.
@@ -233,7 +226,7 @@ class Decoder(srd.Decoder):
 
         self.paritybit[rxtx] = signal
 
-        self.state[rxtx] = GET_STOP_BITS
+        self.state[rxtx] = 'GET STOP BITS'
 
         if parity_ok(self.options['parity_type'], self.paritybit[rxtx],
                      self.databyte[rxtx], self.options['num_data_bits']):
@@ -266,7 +259,7 @@ class Decoder(srd.Decoder):
                      ['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]])
             # TODO: Abort? Ignore the frame? Other?
 
-        self.state[rxtx] = WAIT_FOR_START_BIT
+        self.state[rxtx] = 'WAIT FOR START BIT'
 
         # TODO: Fix range.
         self.put(self.samplenum, self.samplenum, self.out_proto,
@@ -293,15 +286,15 @@ class Decoder(srd.Decoder):
             for rxtx in (RX, TX):
                 signal = rx if (rxtx == RX) else tx
 
-                if self.state[rxtx] == WAIT_FOR_START_BIT:
+                if self.state[rxtx] == 'WAIT FOR START BIT':
                     self.wait_for_start_bit(rxtx, self.oldbit[rxtx], signal)
-                elif self.state[rxtx] == GET_START_BIT:
+                elif self.state[rxtx] == 'GET START BIT':
                     self.get_start_bit(rxtx, signal)
-                elif self.state[rxtx] == GET_DATA_BITS:
+                elif self.state[rxtx] == 'GET DATA BITS':
                     self.get_data_bits(rxtx, signal)
-                elif self.state[rxtx] == GET_PARITY_BIT:
+                elif self.state[rxtx] == 'GET PARITY BIT':
                     self.get_parity_bit(rxtx, signal)
-                elif self.state[rxtx] == GET_STOP_BITS:
+                elif self.state[rxtx] == 'GET STOP BITS':
                     self.get_stop_bits(rxtx, signal)
                 else:
                     raise Exception('Invalid state: %d' % self.state[rxtx])
diff --git a/decoders/usb/usb.py b/decoders/usb/usb.py
index 99dd4b5..bd402dd 100644
--- a/decoders/usb/usb.py
+++ b/decoders/usb/usb.py
@@ -22,15 +22,12 @@
 
 import sigrokdecode as srd
 
-# States
-SE0, J, K, SE1 = 0, 1, 2, 3
-
-# ...
+# Symbols (used as states of our state machine, too)
 syms = {
-        (0, 0): SE0,
-        (1, 0): J,
-        (0, 1): K,
-        (1, 1): SE1,
+        (0, 0): 'SE0',
+        (1, 0): 'J',
+        (0, 1): 'K',
+        (1, 1): 'SE1',
 }
 
 # ...
@@ -118,7 +115,7 @@ class Decoder(srd.Decoder):
                             'decoding, need at least 48MHz' % self.rate)
 
         # Initialise decoder state.
-        self.sym = J
+        self.sym = 'J'
         self.scount = 0
         self.packet = ''
 
@@ -144,12 +141,12 @@ class Decoder(srd.Decoder):
                 continue
 
             # How many bits since the last transition?
-            if self.packet != '' or self.sym != J:
+            if self.packet != '' or self.sym != 'J':
                 bitcount = int((self.scount - 1) * 12000000 / self.rate)
             else:
                 bitcount = 0
 
-            if self.sym == SE0:
+            if self.sym == 'SE0':
                 if bitcount == 1:
                     # End-Of-Packet (EOP)
                     self.put(0, 0, self.out_ann,
@@ -166,7 +163,7 @@ class Decoder(srd.Decoder):
             self.packet += '1' * bitcount
 
             # Handle bit stuffing.
-            if bitcount < 6 and sym != SE0:
+            if bitcount < 6 and sym != 'SE0':
                 self.packet += '0'
             elif bitcount > 6:
                 self.put(0, 0, self.out_ann, [0, ['BIT STUFF ERROR']])