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authorUwe Hermann <uwe@hermann-uwe.de>2014-08-16 21:35:26 +0200
committerUwe Hermann <uwe@hermann-uwe.de>2014-08-16 21:37:21 +0200
commit00bdc23e73fc3af5a7656ae584216330e4a31556 (patch)
treeef2ebd833bf04d0e5ab18d66f8a6ae960620eafb
parent7d74799011f28796bbb8165dc3bcd4c8cca12052 (diff)
downloadlibsigrokdecode-00bdc23e73fc3af5a7656ae584216330e4a31556.tar.gz
libsigrokdecode-00bdc23e73fc3af5a7656ae584216330e4a31556.zip
ds1307: Warn about (and ignore) non-DS1307 traffic.
-rw-r--r--decoders/ds1307/pd.py23
1 files changed, 19 insertions, 4 deletions
diff --git a/decoders/ds1307/pd.py b/decoders/ds1307/pd.py
index ca6faf6..800f7a0 100644
--- a/decoders/ds1307/pd.py
+++ b/decoders/ds1307/pd.py
@@ -44,6 +44,8 @@ rates = {
0b11: '32768kHz',
}
+DS1307_I2C_ADDRESS = 0x68
+
def regs_and_bits():
l = [('reg-' + r.lower(), r + ' register') for r in regs]
l += [('bit-' + re.sub('\/| ', '-', b).lower(), b + ' bit') for b in bits]
@@ -67,11 +69,13 @@ class Decoder(srd.Decoder):
('write-datetime', 'Write date/time'),
('reg-read', 'Register read'),
('reg-write', 'Register write'),
+ ('warnings', 'Warnings'),
)
annotation_rows = (
('bits', 'Bits', tuple(range(9, 24))),
('regs', 'Registers', tuple(range(9))),
('date-time', 'Date/time', (24, 25, 26, 27)),
+ ('warnings', 'Warnings', (28,)),
)
def __init__(self, **kwargs):
@@ -193,6 +197,13 @@ class Decoder(srd.Decoder):
if self.reg > 0x3f:
self.reg = 0
+ def is_correct_chip(self, addr):
+ if addr == DS1307_I2C_ADDRESS:
+ return True
+ self.put(self.block_start_sample, self.es, self.out_ann,
+ [28, ['Ignoring non-DS1307 data (slave 0x%02X)' % addr]])
+ return False
+
def decode(self, ss, es, data):
cmd, databyte = data
@@ -214,9 +225,11 @@ class Decoder(srd.Decoder):
self.block_start_sample = ss
elif self.state == 'GET SLAVE ADDR':
# Wait for an address write operation.
- # TODO: We should only handle packets to the RTC slave (0x68).
if cmd != 'ADDRESS WRITE':
return
+ if not self.is_correct_chip(databyte):
+ self.state = 'IDLE'
+ return
self.state = 'GET REG ADDR'
elif self.state == 'GET REG ADDR':
# Wait for a data write (master selects the slave register).
@@ -237,10 +250,12 @@ class Decoder(srd.Decoder):
self.state = 'IDLE'
elif self.state == 'READ RTC REGS':
# Wait for an address read operation.
- # TODO: We should only handle packets to the RTC slave (0x68).
- if cmd == 'ADDRESS READ':
- self.state = 'READ RTC REGS2'
+ if cmd != 'ADDRESS READ':
+ return
+ if not self.is_correct_chip(databyte):
+ self.state = 'IDLE'
return
+ self.state = 'READ RTC REGS2'
elif self.state == 'READ RTC REGS2':
if cmd == 'DATA READ':
self.handle_reg(databyte)