From 3c35aaa05492cfa60c9482634987b50c5b7b2d38 Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Sun, 21 Oct 2018 18:12:41 +0200 Subject: spiflash: Updates due to recent PD chages. --- .../test/spiflash/winbond_w25q80dv_chip_erase_and_writes_start.output | 1 + 1 file changed, 1 insertion(+) (limited to 'decoder/test/spiflash/winbond_w25q80dv_chip_erase_and_writes_start.output') diff --git a/decoder/test/spiflash/winbond_w25q80dv_chip_erase_and_writes_start.output b/decoder/test/spiflash/winbond_w25q80dv_chip_erase_and_writes_start.output index 436b0a7..701f126 100644 --- a/decoder/test/spiflash/winbond_w25q80dv_chip_erase_and_writes_start.output +++ b/decoder/test/spiflash/winbond_w25q80dv_chip_erase_and_writes_start.output @@ -31,6 +31,7 @@ Status register writes are allowed. " 631-648 spiflash: field: "Status register" 611-648 spiflash: rdsr: "Command: Read status register (RDSR)" "Command: Read status register" "Cmd: Read status register" "Cmd: RDSR" "RDSR" +669-687 spiflash: ce: "Command: Chip erase (CE)" "Command: Chip erase" "Cmd: Chip erase" "Cmd: CE" "CE" 712-729 spiflash: field: "Command: Read status register (RDSR)" "Command: Read status register" "Cmd: Read status register" "Cmd: RDSR" "RDSR" 733-750 spiflash: bit: "Write operation in progress. Internal write enable latch is set. -- cgit v1.2.3-54-g00ecf