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Diffstat (limited to 'decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output')
-rw-r--r--decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output9
1 files changed, 9 insertions, 0 deletions
diff --git a/decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output b/decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output
new file mode 100644
index 0000000..50f9f85
--- /dev/null
+++ b/decoder/test/spiflash/winbond_w25q80dv_ce_without_wren.output
@@ -0,0 +1,9 @@
+8-25 spiflash: field: "Command: Read status register (RDSR)" "Command: Read status register" "Cmd: Read status register" "Cmd: RDSR" "RDSR"
+28-45 spiflash: bit: "No write operation in progress.
+Internal write enable latch is set.
+Block protection bits (BP3-BP0): 0x0.
+Device is not in continuously program mode (CP mode).
+Status register writes are allowed.
+"
+28-45 spiflash: field: "Status register"
+8-45 spiflash: rdsr: "Command: Read status register (RDSR)" "Command: Read status register" "Cmd: Read status register" "Cmd: RDSR" "RDSR"