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| author | Gerhard Sittig <gerhard.sittig@gmx.net> | 2018-01-11 07:05:34 +0100 |
|---|---|---|
| committer | Gerhard Sittig <gerhard.sittig@gmx.net> | 2018-01-11 07:05:34 +0100 |
| commit | 913b372366bc0cffd7bcbacb7b487c7a157db09c (patch) | |
| tree | 2f327f295969490fba8a967ee84218184486d259 /decoder/test/ssi32/ssi32_watchdog.output | |
| parent | 3f0b1d31e4c2e5965e1ca795f673b1ddd1220a2d (diff) | |
| download | sigrok-test-913b372366bc0cffd7bcbacb7b487c7a157db09c.tar.gz sigrok-test-913b372366bc0cffd7bcbacb7b487c7a157db09c.zip | |
counter: use HD44780 dump to check counter's reset_edge option
Resetting counters depending on the LCD controller's R/S signal yields
numbers that correspond to byte sequences that either "control" hardware
(register access) or carry "data" (display text).
Provide a test case for the rising edge of RESET. Existing cases already
covered the falling edge of RESET which is the default.
Diffstat (limited to 'decoder/test/ssi32/ssi32_watchdog.output')
0 files changed, 0 insertions, 0 deletions