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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2015-12-25 17:23:36 +0100 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2015-12-27 23:03:43 +0100 |
| commit | 7974d8f42cc1629aa852b9c535b718d4fc8773e0 (patch) | |
| tree | 7b699c35042ebd542da2f56b3226b5a59422fcbe /decoder/test/parallel/test.conf | |
| parent | dd9648d4c3235317cb8b36c88448f5f14c738a6b (diff) | |
| download | sigrok-test-7974d8f42cc1629aa852b9c535b718d4fc8773e0.tar.gz sigrok-test-7974d8f42cc1629aa852b9c535b718d4fc8773e0.zip | |
Add OUTPUT_PYTHON test-cases for all PDs.
Diffstat (limited to 'decoder/test/parallel/test.conf')
| -rw-r--r-- | decoder/test/parallel/test.conf | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/decoder/test/parallel/test.conf b/decoder/test/parallel/test.conf index e894ee2..b6dd18c 100644 --- a/decoder/test/parallel/test.conf +++ b/decoder/test/parallel/test.conf @@ -2,18 +2,22 @@ test incremental_8ch_short_noclock protocol-decoder parallel channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7 input misc/demo/incremental_8ch_short.sr output parallel annotation match incremental_8ch_short_noclock.output + output parallel python match incremental_8ch_short_noclock.python test incremental_8ch_short_clock protocol-decoder parallel channel clk=0 channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7 input misc/demo/incremental_8ch_short.sr output parallel annotation match incremental_8ch_short_clock.output + output parallel python match incremental_8ch_short_clock.python test incremental_8ch_long_noclock protocol-decoder parallel channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7 input misc/demo/incremental_8ch_long.sr output parallel annotation match incremental_8ch_long_noclock.output + output parallel python match incremental_8ch_long_noclock.python test incremental_8ch_long_clock protocol-decoder parallel channel clk=0 channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7 input misc/demo/incremental_8ch_long.sr output parallel annotation match incremental_8ch_long_clock.output + output parallel python match incremental_8ch_long_clock.python |