From f711de81a725d61c027b45d2fd51efaecb17b4e4 Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Fri, 11 Aug 2017 00:36:44 +0200 Subject: Add a square wave digital + analog capture. --- .../100khz_clock_2logic_1analog.sr | Bin 0 -> 4030 bytes misc/square_wave_analog/README | 19 +++++++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 misc/square_wave_analog/100khz_clock_2logic_1analog.sr create mode 100644 misc/square_wave_analog/README (limited to 'misc') diff --git a/misc/square_wave_analog/100khz_clock_2logic_1analog.sr b/misc/square_wave_analog/100khz_clock_2logic_1analog.sr new file mode 100644 index 0000000..670e8bc Binary files /dev/null and b/misc/square_wave_analog/100khz_clock_2logic_1analog.sr differ diff --git a/misc/square_wave_analog/README b/misc/square_wave_analog/README new file mode 100644 index 0000000..267d41e --- /dev/null +++ b/misc/square_wave_analog/README @@ -0,0 +1,19 @@ +------------------------------------------------------------------------------- +Analog clock signal +------------------------------------------------------------------------------- + +This is a set of example captures of a clock signal (rectangle signal) +generated using a function generator, sampled using an LA/MSO. + + +Logic analyzer setup +-------------------- + +The logic analyzer used was a Noname LHT00SU1 (at 12MHz): + + Probe Signal + ------------------------------- + 1DCH 100kHz clock signal + 2DCH same 100kHz clock signal + 1ACH same 100kHz clock signal + -- cgit v1.2.3-54-g00ecf