From 1cd115bfa6b37e5172dfc3687ea9b70b38430c05 Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Mon, 21 Dec 2015 15:07:09 +0100 Subject: Move 1mhz_clock/ into misc/. --- misc/1mhz_clock/README | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 misc/1mhz_clock/README (limited to 'misc/1mhz_clock/README') diff --git a/misc/1mhz_clock/README b/misc/1mhz_clock/README new file mode 100644 index 0000000..a715bca --- /dev/null +++ b/misc/1mhz_clock/README @@ -0,0 +1,35 @@ +------------------------------------------------------------------------------- +1MHz clock signal +------------------------------------------------------------------------------- + +This is a set of example captures of a digital 1MHz clock signal (rectangle +signal) generated using a function generator, sampled using a logic analyzer. + + +Logic analyzer setup +-------------------- + +The logic analyzer used was a Braintechnology USB-LPS (at 12MHz): + + Probe Signal + ----------------------------- + 1 1MHz clock signal + + +Data +---- + +The sigrok command line used was: + + sigrok-cli --driver fx2lafw -d samplerate=12mhz --time 1s \ + -o -p XXXX + +XXXX specifies how many probes to sample/save: + + - 1 signal: -p 1 + - 4 signals: -p 1-4 + - 7 signals: -p 1-7 + - 8 signals: -p 1-8 + - 9 signals: -p 1-9 + - 16 signals: -p 1-16 + -- cgit v1.2.3-70-g09d2