From 84d7eaee978d076471cd25e561cdc250ef93890b Mon Sep 17 00:00:00 2001 From: fenugrec Date: Wed, 9 Mar 2016 15:12:41 -0500 Subject: Added Renesas/Hitachi AUD Branch Trace dump --- aud/README | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ aud/audgen-01.sr | Bin 0 -> 549 bytes 2 files changed, 50 insertions(+) create mode 100644 aud/README create mode 100644 aud/audgen-01.sr (limited to 'aud') diff --git a/aud/README b/aud/README new file mode 100644 index 0000000..2c4bfb3 --- /dev/null +++ b/aud/README @@ -0,0 +1,50 @@ +------------------------------------------------------------------------------- +Renesas/Hitachi AUD (Advanced User Debugger) +------------------------------------------------------------------------------- + +This is a set of example captures of the Renesas/Hitachi AUD (Advanced User +Debugger) protocol. + +Details: +http://www.renesas.eu/products/mpumcu/superh/sh7050/sh7058/Documentation.jsp +("rej09b0046 - SH7058 Hardware manual") + + +Logic analyzer setup +-------------------- + + Probe Pin + --------------- + 1 AUDCK + 2 nAUDSYNC + 3 AUDATA3 + 4 AUDATA2 + 5 AUDATA1 + 6 AUDATA0 + +The audgen-* files are artificially generated thus: + + - audgen-01.v is written in Verilog; due to limitations in sigrok only + single-bit values are output. + - Icarus Verilog is run to create a VCD dump: + - "iverilog audgen-01.v" + - "./a.out" (created by iverilog) + - The resulting VCD can probably be opened directly by PulseView, but is + here converted to a .sr dump. + +AUD traffic can be challenging to capture because it is clocked out at the +MCU's clock frequency (20MHz typical). This requires an LA capable of either: + + - Timing analysis on 6 channels (clock, sync, data3..0) at >= 80MSps + (40MSps gives very inconsistent results) + - State analysis @ 20MHz, this would be "easy" but cheap hardware like + Logic/Logic16 can't do it. + + +Data +---- + +Example to view decoded output: + + sigrok-cli -i audgen-01.sr -P aud:audck=AUDCK:naudsync=nAUDSYNC:audata3=AUDATA3:audata2=AUDATA2:audata1=AUDATA1:audata0=AUDATA0 + diff --git a/aud/audgen-01.sr b/aud/audgen-01.sr new file mode 100644 index 0000000..5b102a6 Binary files /dev/null and b/aud/audgen-01.sr differ -- cgit v1.2.3-54-g00ecf