From b0ac80e2f0a147ddaeab525604d8b0cacf0fd6cd Mon Sep 17 00:00:00 2001 From: Gerhard Sittig Date: Fri, 22 Dec 2017 13:55:45 +0100 Subject: parallel: unify decode() code paths with and without clock signal Instead of implementing two main loops for operation in the presence and in the absence of a clock line, use a common main loop which operates on pre-determined wait conditions. --- decoders/parallel/pd.py | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'decoders') diff --git a/decoders/parallel/pd.py b/decoders/parallel/pd.py index 140b7b8..4c09d86 100644 --- a/decoders/parallel/pd.py +++ b/decoders/parallel/pd.py @@ -176,10 +176,11 @@ class Decoder(srd.Decoder): for i in range(1, len(self.optional_channels)): if self.has_channel(i): conds.append({i: 'e'}) - while True: - self.handle_bits(self.wait(conds)[1:]) else: # Sample on the rising or falling CLK edge (depends on config). - while True: - pins = self.wait({0: self.options['clock_edge'][0]}) - self.handle_bits(pins[1:]) + edge = self.options['clock_edge'][0] + conds = [{0: edge}] + + while True: + pins = self.wait(conds) + self.handle_bits(pins[1:]) -- cgit v1.2.3-70-g09d2