From 2e3e0840d6cc8ad16b9964dcf5615371591e7f9f Mon Sep 17 00:00:00 2001
From: Vesa-Pekka Palmu <vpalmu@depili.fi>
Date: Thu, 18 Oct 2018 01:56:26 +0300
Subject: spiflash: Bugfix: WRSR was using miso for register decode
---
decoders/spiflash/pd.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
(limited to 'decoders/spiflash/pd.py')
diff --git a/decoders/spiflash/pd.py b/decoders/spiflash/pd.py
index 304545f..3d525b9 100644
--- a/decoders/spiflash/pd.py
+++ b/decoders/spiflash/pd.py
@@ -246,12 +246,12 @@ class Decoder(srd.Decoder):
self.emit_cmd_byte()
elif self.cmdstate == 2:
# Byte 2: Master sends status register 1.
- self.putx([Ann.BIT, [decode_status_reg(miso)]])
+ self.putx([Ann.BIT, [decode_status_reg(mosi)]])
self.putx([Ann.FIELD, ['Status register 1']])
elif self.cmdstate == 3:
# Byte 3: Master sends status register 2.
# TODO: Decode status register 2 correctly.
- self.putx([Ann.BIT, [decode_status_reg(miso)]])
+ self.putx([Ann.BIT, [decode_status_reg(mosi)]])
self.putx([Ann.FIELD, ['Status register 2']])
self.es_cmd = self.es
self.putc([Ann.WRSR, self.cmd_ann_list()])
--
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