From cd287c56af4e005e36faa26a88f6ef6dcbb2c902 Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Fri, 18 May 2012 21:42:29 +0200 Subject: srd: MX25Lxx05D: Fix inverted SRWD bit handling. --- decoders/mx25lxx05d/mx25lxx05d.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'decoders/mx25lxx05d/mx25lxx05d.py') diff --git a/decoders/mx25lxx05d/mx25lxx05d.py b/decoders/mx25lxx05d/mx25lxx05d.py index a5dab2e..1d41fd4 100644 --- a/decoders/mx25lxx05d/mx25lxx05d.py +++ b/decoders/mx25lxx05d/mx25lxx05d.py @@ -113,7 +113,7 @@ def decode_status_reg(data): ret += 'Device is %sin continuously program mode (CP mode).\n' % s # Bits[7:7]: SRWD (status register write disable) - s = '' if (data & (1 << 7)) else 'not ' + s = 'not ' if (data & (1 << 7)) else '' ret += 'Status register writes are %sallowed.\n' % s return ret -- cgit v1.2.3-70-g09d2