From 8eafa2613d2541e934a04874cd35cbc944c3168b Mon Sep 17 00:00:00 2001
From: Uwe Hermann <uwe@hermann-uwe.de>
Date: Mon, 13 Jan 2014 23:26:36 +0100
Subject: parallel: Make CLK probe optional.
When no CLK probe is supplied to this PD, handle any transition on
any of the supplied data probes as if there had been a CLK transition.
(based on a suggestion/patch by "bmx" from the #sigrok channel, thanks!)
---
decoders/parallel/__init__.py | 6 +++++-
decoders/parallel/pd.py | 11 ++++++-----
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/decoders/parallel/__init__.py b/decoders/parallel/__init__.py
index a338c43..ea55077 100644
--- a/decoders/parallel/__init__.py
+++ b/decoders/parallel/__init__.py
@@ -20,7 +20,11 @@
'''
This protocol decoder can decode synchronous parallel buses with various
-number of data bits/probes and one clock line.
+number of data bits/probes and one (optional) clock line.
+
+If no clock line is supplied, the decoder works slightly differently in
+that it interprets every transition on any of the supplied data probes
+like there had been a clock transition.
It is required to use the lowest data probes, and use consecutive ones.
For example, for a 4-bit sync parallel bus, probes D0/D1/D2/D3 (and CLK)
diff --git a/decoders/parallel/pd.py b/decoders/parallel/pd.py
index e766ac1..c31718f 100644
--- a/decoders/parallel/pd.py
+++ b/decoders/parallel/pd.py
@@ -57,7 +57,7 @@ Packet:
'''
def probe_list(num_probes):
- l = []
+ l = [{'id': 'clk', 'name': 'CLK', 'desc': 'Clock line'}]
for i in range(num_probes):
d = {'id': 'd%d' % i, 'name': 'D%d' % i, 'desc': 'Data line %d' % i}
l.append(d)
@@ -72,9 +72,7 @@ class Decoder(srd.Decoder):
license = 'gplv2+'
inputs = ['logic']
outputs = ['parallel']
- probes = [
- {'id': 'clk', 'name': 'CLK', 'desc': 'Clock line'},
- ]
+ probes = []
optional_probes = probe_list(8)
options = {
'clock_edge': ['Clock edge to sample on', 'rising'],
@@ -187,7 +185,10 @@ class Decoder(srd.Decoder):
# State machine.
if self.state == 'IDLE':
- self.find_clk_edge(pins[0], pins[1:])
+ if pins[0] not in (0, 1):
+ self.handle_bits(pins[1:])
+ else:
+ self.find_clk_edge(pins[0], pins[1:])
else:
raise Exception('Invalid state: %s' % self.state)
--
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